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    Wireless Communication Device with Integrated Ferrite Shield and Antenna, and Methods of Manufacturing the Same
    5.
    发明申请
    Wireless Communication Device with Integrated Ferrite Shield and Antenna, and Methods of Manufacturing the Same 有权
    具有集成铁氧体屏蔽和天线的无线通信设备及其制造方法

    公开(公告)号：US20170040665A1

    公开(公告)日：2017-02-09

    申请号：US15230348

    申请日：2016-08-05

    Applicant: Mao TAKASHIMA ,  Aditi CHANDRA ,  Somnath MUKHERJEE ,  Gloria WONG ,  Khanh VAN TU ,  Joey LI ,  Anton POPIOLEK ,  Arvind KAMATH

    Inventor： Mao TAKASHIMA ,  Aditi CHANDRA ,  Somnath MUKHERJEE ,  Gloria WONG ,  Khanh VAN TU ,  Joey LI ,  Anton POPIOLEK ,  Arvind KAMATH

    IPC: H01Q1/22 ,  H01Q1/52 ,  H01Q17/00

    CPC classification number: H01Q1/2291 ,  H01Q7/06

    Abstract: A wireless communication device and methods of manufacturing and using the same are disclosed. The wireless communication device includes a substrate with an antenna and/or inductor thereon, a patterned ferrite layer overlapping the antenna and/or inductor, and a capacitor electrically connected to the antenna and/or inductor. The wireless communication device may further include an integrated circuit including a receiver configured to convert a first wireless signal to an electric signal and a transmitter configured to generate a second wireless signal, the antenna being configured to receive the first wireless signal and transmit or broadcast the second wireless signal. The patterned ferrite layer advantageously mitigates the deleterious effect of metal objects in proximity to a reader and/or transponder magnetically coupled to the antenna.

    Abstract translation: 公开了一种无线通信装置及其制造和使用方法。 无线通信设备包括其上具有天线和/或电感器的基板，与天线和/或电感器重叠的图案化铁氧体层，以及电连接到天线和/或电感器的电容器。 无线通信设备还可以包括集成电路，其包括被配置为将第一无线信号转换为电信号的接收机和被配置为生成第二无线信号的发射机，所述天线被配置为接收第一无线信号并发送或广播 第二无线信号。 图案化的铁氧体层有利地减轻了金属物体靠近与天线磁耦合的读取器和/或应答器的有害影响。

    Printed non-volatile memory
    7.
    发明授权
    Printed non-volatile memory 有权
    打印的非易失性存储器

    公开(公告)号：US08796774B2

    公开(公告)日：2014-08-05

    申请号：US13585673

    申请日：2012-08-14

    Applicant: Arvind Kamath ,  Patrick Smith ,  James Montague Cleeves

    Inventor： Arvind Kamath ,  Patrick Smith ,  James Montague Cleeves

    IPC: H01L29/66 ,  H01L29/788

    CPC classification number: H01L21/28518 ,  H01L21/288 ,  H01L21/76801 ,  H01L21/76895 ,  H01L27/115 ,  H01L27/11558 ,  H01L27/1292 ,  H01L29/66757 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.

    Abstract translation: 公开了一种非易失性存储单元，其具有位于相同水平位置并且间隔开预定距离的第一和第二半岛，所述第一半岛具有提供控制栅极和所述第二半岛岛提供源极和漏极端子; 在所述第一半导体岛的至少一部分上的栅介质层; 在所述第二半导体岛的至少一部分上的隧道介电层; 至少部分栅极电介质层和隧道电介质层上的浮栅; 以及与控制栅极以及源极和漏极端子电接触的金属层。 在一个有利的实施例中，可以使用“全印刷”工艺技术来制造非易失性存储单元。

    Printed Dopant Layers
    8.
    发明申请
    Printed Dopant Layers 有权
    印刷掺杂层

    公开(公告)号：US20140094004A1

    公开(公告)日：2014-04-03

    申请号：US13633816

    申请日：2012-10-02

    Applicant: Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zürcher

    Inventor： Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zürcher

    IPC: H01L21/336

    CPC classification number: H01L27/1292 ,  H01L29/66757

    Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.

    Abstract translation: 一种用于制造诸如MOS晶体管的电子器件的方法，包括以下步骤：在电功能衬底上形成多个半导体岛，在第一半导体岛子集上或第二子体上印刷第一介电层， 在半导体岛的第二子集上或之上，以及退火。 第一介电层包含第一掺杂剂，并且（任选的）第二介电层包含不同于第一掺杂剂的第二掺杂剂。 电介质层，半导体岛和衬底被充分退火以将第一掺杂剂扩散到半导体岛的第一子集中，并且当存在时将第二掺杂剂扩散到半导体岛的第二子集中。

    DIFFUSION BARRIER COATED SUBSTRATES AND METHODS OF MAKING THE SAME
    9.
    发明申请
    DIFFUSION BARRIER COATED SUBSTRATES AND METHODS OF MAKING THE SAME 有权
    扩散阻挡层涂覆基板及其制造方法

    公开(公告)号：US20130243940A1

    公开(公告)日：2013-09-19

    申请号：US13873156

    申请日：2013-04-29

    Applicant: Arvind KAMATH ,  Michael KOCSIS ,  Kevin MCCARTHY ,  Gloria WONG ,  Jiang LI

    Inventor： Arvind KAMATH ,  Michael KOCSIS ,  Kevin MCCARTHY ,  Gloria WONG ,  Jiang LI

    IPC: H01F5/00 ,  H01Q7/00 ,  H01F41/04

    CPC classification number: H01F5/003 ,  H01F5/00 ,  H01F41/041 ,  H01L27/1218 ,  H01L27/1292 ,  H01L29/78603 ,  H01L29/78681 ,  H01L29/7869 ,  H01Q1/2283 ,  H01Q7/00

    Abstract: Devices on a diffusion barrier coated metal substrates, and methods of making the same are disclosed. The devices include a metal substrate, a diffusion barrier layer on the metal substrate, one or more insulator layers on the diffusion barrier layer, and an antenna and/or inductor on the one or more insulator layer(s). The method includes forming a diffusion barrier layer on the metal substrate, forming one or more insulator layers on the diffusion barrier layer; and forming an antenna and/or inductor on an uppermost one of the insulator layer(s). The antenna and/or inductor is electrically connected to at least one of the diffusion barrier layer and/or the metal substrate. Such diffusion barrier coated substrates prevent diffusion of metal atoms from the metal substrate into device layers formed thereon.

    Abstract translation: 公开了扩散阻挡涂层金属基板上的器件及其制造方法。 这些器件包括金属衬底，金属衬底上的扩散阻挡层，扩散阻挡层上的一个或多个绝缘体层，以及一个或多个绝缘体层上的天线和/或电感器。 该方法包括在金属基板上形成扩散阻挡层，在扩散阻挡层上形成一个或多个绝缘体层; 以及在所述绝缘体层的最上面形成天线和/或电感器。 天线和/或电感器电连接到扩散阻挡层和/或金属衬底中的至少一个。 这种扩散阻挡涂层的基底防止金属原子从金属基底扩散到其上形成的器件层。

    Profile engineered, electrically active thin film devices
    10.
    发明授权
    Profile engineered, electrically active thin film devices 有权
    型材设计，电活性薄膜器件

    公开(公告)号：US08426905B2

    公开(公告)日：2013-04-23

    申请号：US12243880

    申请日：2008-10-01

    Applicant: Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    Inventor： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    IPC: H01L29/788

    CPC classification number: H01L21/36 ,  C23C18/08 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1295 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/76871 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L28/40 ,  H01L29/0657 ,  H01L29/66143 ,  H01L29/6675 ,  H01L29/7881 ,  H01L29/872 ,  H05K1/16 ,  H05K1/162 ,  H05K3/125 ,  H05K2201/098

    Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.

    Abstract translation: 本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法 通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。 平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。 本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。 这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。 均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

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