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54 条记录 (耗时 0.021 秒)

    Multicasting Using a Multitiered Distributed Virtual Bridge Hierarchy
    13.
    发明申请
    Multicasting Using a Multitiered Distributed Virtual Bridge Hierarchy 有权
    使用多层分布式虚拟网桥层次结构进行组播

    公开(公告)号：US20110261815A1

    公开(公告)日：2011-10-27

    申请号：US12767481

    申请日：2010-04-26

    申请人： William J. Armstrong ,  Claude Basso ,  Josep Cors ,  Kyle A. Lucke ,  David A. Shedivy ,  Kenneth M. Valk ,  Bruce M. Walk

    发明人： William J. Armstrong ,  Claude Basso ,  Josep Cors ,  Kyle A. Lucke ,  David A. Shedivy ,  Kenneth M. Valk ,  Bruce M. Walk

    IPC分类号： H04L12/56

    CPC分类号： H04L12/4625 ,  H04L45/16

    摘要： Systems and methods to multicast data frames are provided. A particular apparatus includes a plurality of computing nodes and a distributed virtual bridge. The distributed virtual bridge includes a plurality of bridge elements coupled to the plurality of computing nodes. The plurality of bridge elements are configured to forward a copy of a multicast data frame to the plurality of computing nodes using group member information associated with addresses of the plurality of server computers. A controlling bridge coupled to the plurality of bridge elements is configured to communicate the group member information to the plurality of bridge elements.

    摘要翻译： 提供了组播数据帧的系统和方法。 特定装置包括多个计算节点和分布式虚拟桥。 分布式虚拟桥包括耦合到多个计算节点的多个桥元件。 多个桥元件被配置为使用与多个服务器计算机的地址相关联的组成员信息将多播数据帧的副本转发到多个计算节点。 耦合到所述多个桥接元件的控制桥被配置为将所述组成员信息传递到所述多个桥接元件。

    Implementing Control Using A Single Path In A Multiple Path Interconnect System
    14.
    发明申请
    Implementing Control Using A Single Path In A Multiple Path Interconnect System 审中-公开
    在多路径互连系统中使用单个路径实现控制

    公开(公告)号：US20110246692A1

    公开(公告)日：2011-10-06

    申请号：US12751469

    申请日：2010-03-31

    申请人： Kenneth M. Valk ,  Bruce M. Walk

    发明人： Kenneth M. Valk ,  Bruce M. Walk

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4022 ,  H04L45/304

    摘要： A method and circuit for implementing control using a single path in a multiple path interconnect system, and a design structure on which the subject circuit resides are provided. Control TL messages include control information to be transferred between a respective source transport layer of a source interconnect chip and a destination transport layer of a destination interconnect chip. Each transport layer (TL) includes a TL message port identifying a port used to send and receive control TL messages for a pair of source TL and destination TL. The respective TL message port of the pair of source TL and destination TL defines the single path used for control messages.

    摘要翻译： 一种用于在多路径互连系统中实现使用单个路径的控制的方法和电路，以及设置有该主题电路所在的设计结构。 控制TL消息包括要在源互连芯片的相应源传输层和目的地互连芯片的目的地传输层之间传送的控制信息。 每个传输层（TL）包括标识用于发送和接收一对源TL和目的地TL的控制TL消息的端口的TL消息端口。 源TL和目的地TL对的各个TL消息端口定义了用于控制消息的单个路径。

    System and method for providing multiple virtual host channel adapters using virtual switches
    15.
    发明授权
    System and method for providing multiple virtual host channel adapters using virtual switches 有权
    使用虚拟交换机提供多个虚拟主机通道适配器的系统和方法

    公开(公告)号：US07581021B2

    公开(公告)日：2009-08-25

    申请号：US11100846

    申请日：2005-04-07

    申请人： Richard K. Errickson ,  David Craddock ,  Thomas A. Gregg ,  Donald W. Schmidt ,  Jeffrey M. Turner ,  Bruce M. Walk

    发明人： Richard K. Errickson ,  David Craddock ,  Thomas A. Gregg ,  Donald W. Schmidt ,  Jeffrey M. Turner ,  Bruce M. Walk

    IPC分类号： G06F15/173

    CPC分类号： H04L49/35 ,  H04L49/30 ,  H04L49/358 ,  H04L49/70 ,  H04L67/1097

    摘要： A processor node of a network is provided which includes one or more processors and a virtualized channel adapter. The virtualized channel adapter is operable to reference a table to determine whether a destination of the communication is supported by the virtualized channel adapter. When the destination is supported for routing via hardware, the virtualized channel adapter is operable to route the communication via hardware to at least one of a physical port and a logical port of the virtualized channel adapter. Otherwise, when the destination is not supported for routing via hardware, the virtualized channel adapter is operable to route the communication via firmware to a virtual port of the virtualized channel adapter. A corresponding method and a recording medium having information recorded thereon for performing such method are also provided herein.

    摘要翻译： 提供网络的处理器节点，其包括一个或多个处理器和虚拟通道适配器。 虚拟化通道适配器可操作以引用表以确定通信的目的地是否由虚拟化通道适配器支持。 当目的地被支持通过硬件进行路由时，虚拟化信道适配器可操作以经由硬件将通信路由到虚拟化信道适配器的物理端口和逻辑端口中的至少一个。 否则，当目的地不支持通过硬件进行路由时，虚拟化信道适配器可操作地将通过固件的通信路由到虚拟化信道适配器的虚拟端口。 本文还提供了相应的方法和记录介质，用于执行这种方法。

    Implementing end-to-end credit management for enhanced large packet reassembly
    19.
    发明授权
    Implementing end-to-end credit management for enhanced large packet reassembly 失效
    实施端到端信用管理，增强大包重组

    公开(公告)号：US08675683B2

    公开(公告)日：2014-03-18

    申请号：US12764175

    申请日：2010-04-21

    申请人： Kenneth M. Valk ,  Bruce M. Walk

    发明人： Kenneth M. Valk ,  Bruce M. Walk

    IPC分类号： H04J3/24

    CPC分类号： H04L47/39 ,  H04L47/365

    摘要： A method and circuit for implementing end-to-end credit management for enhanced large packet reassembly in an interconnect system, and a design structure on which the subject circuit resides are provided. A transport layer provides buffering and credit control for a super packet received from a source device. A source transport layer sends an End-to-End (ETE) credit request message to a destination transport layer for an outstanding super packet transmission to a destination device. The destination transport layer grants credit to allow at least one source to send a super packet to the destination. The source transport layer fragments the super packet into multiple packets and sends all packets of the super packet only responsive to the credit request being granted by the destination transport layer that is needed to send all packets of the super packet.

    摘要翻译： 一种用于实现端到端信用管理以在互连系统中增强大分组重组的方法和电路，以及提供了主题电路所在的设计结构。 传输层为从源设备接收的超级分组提供缓冲和信用控制。 源传输层向目的地传输层发送端到端（ETE）信用请求消息，以发送到目的设备的未完成的超级分组传输。 目的地传输层授予信用以允许至少一个源向目的地发送超级分组。 源传输层将超级分组分解成多个分组，并且只响应发送所有超级分组的所有分组所需的目的传输层授予的信用请求，发送超分组的所有分组。