公开(公告)号：US20220352369A1

公开(公告)日：2022-11-03

申请号：US17761510

申请日：2020-08-20

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO.,LTD.

Inventor： JING ZHU ,  GUICHUANG ZHU ,  NAILONG HE ,  SEN ZHANG ,  SHAOHONG LI ,  WEIFENG SUN ,  LONGXING SHI

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10

Abstract: A laterally double-diffused metal oxide semiconductor device is provided, including: a drift region (3) having a first conductivity type; a first body region (10) disposed on the drift region (3) and having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; a first conductivity type region (13) disposed in the first body region (10); a second body region (12) disposed in the first conductivity type region (13) and having the second conductivity type; a source region (11) disposed in the second body region (12) and having the first conductivity type; and a contact region (9) disposed in the first body region (10) and having the second conductivity type.

公开(公告)号：US11462628B2

公开(公告)日：2022-10-04

申请号：US16771168

申请日：2018-11-13

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Guipeng Sun

IPC: H01L31/062 ,  H01L29/76 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device, and a manufacturing method thereof. The method includes: providing a semiconductor substrate provided with a body region, a gate dielectric layer, and a field oxide layer, formed on the semiconductor substrate; forming a gate polycrystalline, the gate polycrystalline covering the gate dielectric layer and the field oxide layer and exposing at least one portion of the field oxide layer; forming a drift region in the semiconductor substrate by ion implantation using a drift region masking layer as a mask, removing the exposed portion of the field oxide layer by further using the drift region masking layer as the mask to form a first field oxide self-aligned with the gate polycrystalline; forming a source region in the body region, and forming a drain region in the drift region; forming a second field oxide on the semiconductor substrate; and forming a second field plate on the second field oxide.

公开(公告)号：US20220302104A1

公开(公告)日：2022-09-22

申请号：US17639076

申请日：2020-08-06

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Danye LIANG ,  Guangyang WANG

IPC: H01L27/02

Abstract: In one aspect, a bidirectional Electro-Static Discharge (ESD) protection device includes: a first well region, a second well region and a third well region formed in a semiconductor substrate; two or more first injection regions and two or more second injection regions formed in the first well region, and two or more fourth injection regions and two or more fifth injection regions formed in the second well region; and third injection regions formed at a junction of the first well region and the third well region and at a junction of the second well region and the third well region.

公开(公告)号：US20220223692A1

公开(公告)日：2022-07-14

申请号：US17624336

申请日：2020-09-25

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO.,LTD

Inventor： SIYANG LIU ,  NINGBO LI ,  DEJIN WANG ,  KUI XIAO ,  CHI ZHANG ,  SHENG LI ,  XINYI TAO ,  WEIFENG SUN ,  LONGXING SHI

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/872 ,  H01L29/06 ,  H01L21/02

Abstract: A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.

公开(公告)号：US20220037211A1

公开(公告)日：2022-02-03

申请号：US17299380

申请日：2019-12-04

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yuanbao LIAO

IPC: H01L21/8234 ,  H01L27/02

Abstract: The present application relates to a preparation method for a semiconductor device, comprising: sequentially forming an isolating dielectric layer and a doped semiconductor layer of a first conductivity type on a non-primitive cell area of a semiconductor substrate; performing a first conductivity type of well injection by using the semiconductor layer and the isolating dielectric layer as masks, and forming a well area in a primitive cell area; forming an operation structure in the well area, and forming a protection structure in the semiconductor layer; and forming an interlayer dielectric layer on the operation structure and the protection structure, forming a contact hole in the interlayer dielectric layer, forming a metal interconnection layer connected to the contact hole on the interlayer dielectric layer, and connecting the operation structure and the protection structure by means of the metal interconnection layer and the contact hole.

公开(公告)号：US11222888B2

公开(公告)日：2022-01-11

申请号：US16980368

申请日：2019-03-05

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jun Sun

IPC: H01L23/62 ,  H01L27/02 ,  H01L27/07 ,  H01L29/08 ,  H01L29/78 ,  H01L23/60 ,  H01L29/87

Abstract: An anti-static metal oxide semiconductor field effect transistor structure includes an anti-static body structure and a slave metal oxide semiconductor field effect transistor, the anti-static body structure includes: a main metal oxide semiconductor field effect transistor; a first silicon controlled rectifier, an anode thereof being connected to a drain of the main metal oxide semiconductor field effect transistor, a cathode and a control electrode thereof being connected to a source of the main metal oxide semiconductor field effect transistor; and a second silicon controlled rectifier, an anode thereof being connected to the drain of the main metal oxide semiconductor field effect transistor, a cathode thereof being connected to a gate of the main metal oxide semiconductor field effect transistor, a control electrode thereof being connected to the source or the gate of the main metal oxide semiconductor field effect transistor.

公开(公告)号：US11188700B2

公开(公告)日：2021-11-30

申请号：US17053550

申请日：2019-08-15

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Nan Zhang ,  Jing Zhou ,  Hao Wang ,  Zhan Gao ,  Maoqian Zhu ,  Cheng Zhou ,  Zhijin Li ,  Lin Wu ,  Shuming Guo ,  Yong Huang

IPC: G06F30/367 ,  G06F30/392 ,  G06F119/06

Abstract: The present application relates to a resistance simulation method for a power device, comprising: establishing an equivalent resistance model of a power device, wherein the connection relationship of N fingers is equivalent to N resistors Rb connected in parallel, input ends of adjacent resistors Rb are connected by means of a resistor Ra, output ends of adjacent resistors Rb are connected by means of a resistor Rc, R a = 1 N ⁢ R 0 , R c = 1 N ⁢ R 1 , and Rb=RDEV*N+RS+RD, wherein R0 and R1 are respectively resistances of a source metal strip and a drain metal strip, Rs is a metal resistor of a first intermediate layer connecting one source region to the source metal strip, RD is a metal resistor of a second intermediate layer connecting one drain region to the drain metal strip, and RDEV is the channel resistance of the power device; and calculating the resistance of the equivalent resistance model as the resistance of the power device.

公开(公告)号：US11158736B2

公开(公告)日：2021-10-26

申请号：US16890151

申请日：2020-06-02

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Tse-Huang Lo

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A MOSFET structure and a manufacturing method thereof are provided. The structure includes a substrate, a well region of a first conductivity type, a first trench formed on a surface of the well region of the first conductivity type and extending downwards to a well region of a second conductivity type, a source disposed in the well region of the second conductivity type and under the first trench, a gate oxide layer disposed on an inner surface of the first trench, a polysilicon gate disposed on the gate oxide layer, a conductive plug extending downwards from above the first trench and being in contact with the well region of the second conductivity type after extending through the source, an insulation oxide layer filled in the first trench between the conductive plug and the polysilicon gate, and a drain disposed outside the first trench and obliquely above the source.

公开(公告)号：US20210296428A1

公开(公告)日：2021-09-23

申请号：US17263285

申请日：2019-11-11

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Hongfeng Jin

IPC: H01L49/02 ,  H01L23/522

Abstract: An MIM capacitor and a manufacturing method therefor. The manufacturing method comprises: providing a semiconductor substrate, and forming a first metal layer on the semiconductor substrate; forming an anti-reflection layer on the first metal layer; performing photoetching and etching on the first metal layer and the anti-reflection layer so as to define an MIM capacitor region, wherein the first metal layer in the MIM capacitor region serves as a lower electrode plate of the MIM capacitor, and the anti-reflection layer in the MIM capacitor region serves as a dielectric layer of the MIM capacitor; and forming an upper electrode plate of the MIM capacitor on the anti-reflection layer in the MIM capacitor region.

公开(公告)号：US20210249403A1

公开(公告)日：2021-08-12

申请号：US17267835

申请日：2019-08-15

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/866

Abstract: A transient voltage suppression device and a manufacturing method therefor, the transient voltage suppression device including: a substrate, a first conductivity type well region and a second conductivity type well region disposed in the substrate. The first conductivity type well region includes a first well, a second well, and a third well. The second conductivity type well region includes a fourth well that isolates the first well from the second well, and a fifth well that isolates the second well from the third well. The device further includes a Zener diode well region provided in the first well, a first doped region provided in the Zener diode well region, a second doped region provided in the Zener diode well region, a third doped region provided in the second well, a fourth doped region provided in the third well, and a fifth doped region provided in the third well.