公开(公告)号：US07589766B2

公开(公告)日：2009-09-15

申请号：US10659472

申请日：2003-09-10

Applicant: Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

Inventor： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

IPC: H04N5/235 ,  H04N5/238

CPC classification number: H04N5/2352 ,  H04N5/243

Abstract: A selectable threshold multimode gain control apparatus and method for a charge coupled device (CCD) or CMOS imaging system includes an automatic gain control (AGC) circuit which continuously controls gain in said CCD system to produce a mutually continuous combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

Abstract translation: 一种用于电荷耦合器件（CCD）或CMOS成像系统的可选阈值多模增益控制装置和方法，包括一自动增益控制（AGC）电路，其连续地控制所述CCD系统中的增益以产生相互连续的组合目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路以及用于快门增益的快门定时。

公开(公告)号：US20070054629A1

公开(公告)日：2007-03-08

申请号：US10730404

申请日：2003-12-08

Applicant: James Maligeorgos ,  Augusto Marques ,  Lysander Lim ,  G. Tuttle ,  Aslamali Rafi ,  Tod Paulus ,  Gregory Uehara ,  Jeffrey Scott ,  Richard Behrens ,  Donald Kerth ,  G. Vishakhadatta ,  Vishnu Srinivasan ,  Caiyi Wang

Inventor： James Maligeorgos ,  Augusto Marques ,  Lysander Lim ,  G. Tuttle ,  Aslamali Rafi ,  Tod Paulus ,  Gregory Uehara ,  Jeffrey Scott ,  Richard Behrens ,  Donald Kerth ,  G. Vishakhadatta ,  Vishnu Srinivasan ,  Caiyi Wang

IPC: H04B1/38

CPC classification number: H04B1/30 ,  H03J2200/10 ,  H04L27/0002

Abstract: Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry. Automatic frequency control (AFC) circuitry may be integrated with other components of RF circuitry and may generate frequency control signals for the frequency modification circuitry based on, for example, a signal received from a temperature sensor. Digital-to-analog converter (DAC) circuitry may be integrated with other components of RF circuitry to enable all-digital frequency control communications from baseband processor circuitry to RF circuitry.

Abstract translation: 包括生成具有可变频率的参考信号的晶体振荡器电路的收发器电路和频率修改电路的射频（RF）设备的组件可以以各种方式被划分，例如作为一个或多个单独的集成电路。 频率修改电路可以被实现为包括数字控制的晶体振荡器（“DCXO”）电路和晶体的晶体振荡器电路的一部分。 频率修改电路可以包括至少一个可变电容器件，并且可以用于产生具有可调频率的参考信号。 可调参考信号可以被提供给RF装置的其他部件，和/或RF装置可以被配置为向基带处理器电路提供可调参考信号。 自动频率控制（AFC）电路可以与RF电路的其它组件集成，并且可以基于例如从温度传感器接收的信号来生成用于频率修改电路的频率控制信号。 数模转换器（DAC）电路可以与RF电路的其他部件集成，以实现从基带处理器电路到RF电路的全数字频率控制通信。

公开(公告)号：US20060197847A1

公开(公告)日：2006-09-07

申请号：US11415000

申请日：2006-05-01

Applicant: Sandra Johnson ,  Shih-Chung Chao ,  Nadi Itani ,  Caiyi Wang ,  Brannon Harris ,  Ash Prabala ,  Douglas Holberg ,  Alan Hansford ,  Syed Azim ,  David Welland

Inventor： Sandra Johnson ,  Shih-Chung Chao ,  Nadi Itani ,  Caiyi Wang ,  Brannon Harris ,  Ash Prabala ,  Douglas Holberg ,  Alan Hansford ,  Syed Azim ,  David Welland

IPC: H04N5/235

CPC classification number: H04N5/3575 ,  H04N5/335 ,  H04N5/361

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.

公开(公告)号：US06965761B2

公开(公告)日：2005-11-15

申请号：US10358563

申请日：2003-02-05

Applicant: David R. Welland ,  Caiyi Wang

Inventor： David R. Welland ,  Caiyi Wang

IPC: H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/193 ,  H03L7/199 ,  H03L7/23 ,  H04B1/06 ,  H04B1/40 ,  H04B7/00 ,  H03B5/24

CPC classification number: H03L7/193 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/199 ,  H03L7/23 ,  H03L2207/06

Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock. Second, the phase differences between the plurality of phase shifted signals and a divided version of a reference clock may be detected and then converted to the analog control signals.

Abstract translation: 用于合成诸如无线通信信号的高频信号的方法和装置包括具有可变电容电压控制振荡器（VCO）的锁相环（PLL）频率合成器，其具有连续变量的离散可变电容 电容。 离散可变电容可以提供可变电容的粗调谐调整，以补偿电容器和电感器公差，并将输出频率调整为接近期望的频率输出。 连续可变电容可以提供可变电容的微调调整，以将输出频率聚焦以精确地匹配期望的频率输出。 在微调调整期间，PLL可以由多个模拟控制信号控制。 可以通过首先从VCO输出时钟的分割版本产生多个相移信号来导出模拟控制信号。 第二，可以检测多个相移信号和参考时钟的分割版本之间的相位差，然后转换成模拟控制信号。

公开(公告)号：US06741846B1

公开(公告)日：2004-05-25

申请号：US09708339

申请日：2000-11-08

Applicant: David R. Welland ,  Caiyi Wang

Inventor： David R. Welland ,  Caiyi Wang

IPC: H04B700

CPC classification number: H03L7/099 ,  H03L7/085 ,  H03L7/087 ,  H03L7/091 ,  H03L7/187 ,  H03L7/199 ,  H03L7/23

Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may include an analog control loop in which a phase detector circuit and sample and hold circuit are utilized. The output of the sample and hold circuit may be provided to the PLL VCO as VCO input control signals.

公开(公告)号：US06650364B1

公开(公告)日：2003-11-18

申请号：US09075348

申请日：1998-05-08

Applicant: Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

Inventor： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

IPC: H04N5235

CPC classification number: H04N5/2352 ,  H04N5/243

Abstract: A selectable threshold multimode gain control apparatus and method for a charge coupled device (CCD) or CMOS imaging system includes an automatic gain control (AGC) circuit which continuously controls gain in said CCD system to produce a mutually continuous combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

公开(公告)号：US08648653B2

公开(公告)日：2014-02-11

申请号：US12650546

申请日：2009-12-31

Applicant: David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

Inventor： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC: H03K5/00

CPC classification number: H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract translation: 提供一种减少电路干扰的方法和装置。 提供管理策略，以减少参考杂散和电路干扰。 管理策略使用一种或多种减少数字电流，最小化互感，利用场消除，防止泄漏电流和/或管理阻抗的技术的组合。 这些技术可以单独使用，或者优选地彼此组合使用。

公开(公告)号：US08421529B2

公开(公告)日：2013-04-16

申请号：US12650543

申请日：2009-12-31

Applicant: David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

Inventor： David R. Welland ,  Donald A. Kerth ,  Caiyi Wang

IPC: H03K5/00

CPC classification number: H05K9/00 ,  H03L7/18 ,  H05K1/0216 ,  H05K3/10 ,  Y10T29/49124

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

公开(公告)号：US07477879B1

公开(公告)日：2009-01-13

申请号：US11172039

申请日：2005-06-30

Applicant: Ramkishore Ganti ,  Caiyi Wang

Inventor： Ramkishore Ganti ,  Caiyi Wang

IPC: H04B1/40

CPC classification number: H04B1/0475 ,  H04B1/28

Abstract: A transceiver system including a common receiver and transmitter oscillator. The transceiver system may include transmitter circuitry, receiver circuitry, and a first oscillator. The first oscillator may provide a transmit frequency to a mixer in the transmitter circuitry to generate a transmitter RF signal. Furthermore, the first oscillator may also provide the transmit frequency to a first stage mixer in the receiver circuitry to down-convert a receiver RF signal from a receive frequency to an intermediate frequency (IF). The receiver circuitry may include a second oscillator and a second stage mixer. The second oscillator may provide an IF frequency to the second stage mixer to down-convert receiver signals at IF to a lower frequency. The receiver circuitry may filter out transmitter RF feedthrough signals without using a SAW filter. The transmitter circuitry, the receiver circuitry, and the first oscillator may be included in a single IC.

Abstract translation: 一种收发机系统，包括公共接收机和发射机振荡器。 收发机系统可以包括发射机电路，接收机电路和第一振荡器。 第一振荡器可以向发射机电路中的混频器提供发射频率以产生发射机RF信号。 此外，第一振荡器还可以向接收机电路中的第一级混频器提供发射频率，以将接收机RF信号从接收频率下变频到中频（IF）。 接收器电路可以包括第二振荡器和第二级混频器。 第二振荡器可以向第二级混频器提供IF频率以在IF处将接收机信号下变频到较低的频率。 接收器电路可以滤除发射器RF馈通信号而不使用SAW滤波器。 发射机电路，接收机电路和第一振荡器可以被包括在单个IC中。

公开(公告)号：US07376396B2

公开(公告)日：2008-05-20

申请号：US11096133

申请日：2005-03-31

Applicant: David R. Welland ,  Caiyi Wang

Inventor： David R. Welland ,  Caiyi Wang

IPC: H04B1/40 ,  H03C1/52

CPC classification number: H04B1/403

Abstract: A ratiometric transmit path architecture for communication systems and related methods are disclosed. This ratiometric transmit path architecture utilizes a single local oscillator signal and dividers to provide mixing signals for intermediate frequency (IF) mixing circuitry and feedback mixing circuitry, thereby eliminating the need for separate IF and radio frequency (RF) voltage controlled oscillators (VCOs) in prior solutions.

Abstract translation: 公开了用于通信系统和相关方法的比例传输路径架构。 这种比例传输路径架构利用单个本地振荡器信号和分频器来为中频（IF）混频电路和反馈混频电路提供混频信号，从而消除对单独的IF和射频（RF）压控振荡器（VCO）的需要 以前的解决方案。