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公开(公告)号：US08063389B2
公开(公告)日：2011-11-22
申请号：US12403191
申请日：2009-03-12
IPC分类号： H01J37/08
CPC分类号： G21F1/12
摘要： A method of performing an ion implantation is provided. A workpiece is installed in the ion implanter. A wafer is provided in a receiving space within an ion implanter. An ion beam is generated by an ion source of the ion implanter. The bombard of the ion beam is blocked and particles generated during or after conducting the step of generating the ion beam are collected by the workpiece.
摘要翻译： 提供了进行离子注入的方法。 工件安装在离子注入机中。 晶片设置在离子注入机内的接收空间中。 离子束由离子注入机的离子源产生。 离子束的轰击被阻挡，并且在进行产生离子束的步骤期间或之后产生的颗粒被工件收集。
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公开(公告)号：US20110171805A1
公开(公告)日：2011-07-14
申请号：US13027436
申请日：2011-02-15
申请人： Chen-Hua Yu , Cheng-Hung Chang , Chen-Nan Yeh , Yu-Rung Hsu
发明人： Chen-Hua Yu , Cheng-Hung Chang , Chen-Nan Yeh , Yu-Rung Hsu
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/785 , H01L21/76897 , H01L23/485 , H01L29/20 , H01L29/41791 , H01L29/66795 , H01L29/7843 , H01L2029/7858
摘要： System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.
摘要翻译： 公开了用于降低接触电阻并防止由于接触不对准引起的变化的系统和方法。 优选实施例包括具有位于鳍内的源/漏区的非平面晶体管。 层间电介质覆盖非平面晶体管，并且通过层间电介质将触点形成到源/漏区。 接触件优选地与翅片的多个表面接触，以增加接触件和翅片之间的接触面积。
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公开(公告)号：US07910994B2
公开(公告)日：2011-03-22
申请号：US11872546
申请日：2007-10-15
申请人： Chen-Hua Yu , Cheng-Hung Chang , Chen-Nan Yeh , Yu-Rung Hsu
发明人： Chen-Hua Yu , Cheng-Hung Chang , Chen-Nan Yeh , Yu-Rung Hsu
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/785 , H01L21/76897 , H01L23/485 , H01L29/20 , H01L29/41791 , H01L29/66795 , H01L29/7843 , H01L2029/7858
摘要： System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.
摘要翻译： 公开了用于降低接触电阻并防止由于接触不对准引起的变化的系统和方法。 优选实施例包括具有位于鳍内的源/漏区的非平面晶体管。 层间电介质覆盖非平面晶体管，并且通过层间电介质将触点形成到源/漏区。 接触件优选地与翅片的多个表面接触，以增加接触件和翅片之间的接触面积。
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公开(公告)号：US20100185077A1
公开(公告)日：2010-07-22
申请号：US12488987
申请日：2009-06-22
CPC分类号： C25D5/56 , A61B5/0408
摘要： A flexible dry electrode and the manufacturing method thereof are provided. The electrode has an electroplated uneven surface and at least one hole and is made of porous material.
摘要翻译： 提供柔性干电极及其制造方法。 电极具有电镀不平坦表面和至少一个孔，并由多孔材料制成。
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公开(公告)号：US07745890B2
公开(公告)日：2010-06-29
申请号：US11863804
申请日：2007-09-28
申请人： Chen-Hua Yu , Cheng-Tung Lin , Cheng-Hung Chang , Hsiang-Yi Wang , Chen-Nan Yeh
发明人： Chen-Hua Yu , Cheng-Tung Lin , Cheng-Hung Chang , Hsiang-Yi Wang , Chen-Nan Yeh
IPC分类号： H01L29/78
CPC分类号： H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L27/092
摘要： A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-κ dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-κ dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-κ dielectric and the fully silicided layer.
摘要翻译： 公开了一种用于混合金属全硅化（FUSI）栅极结构的半导体器件和系统。 所述半导体系统包括PMOS栅极结构，所述PMOS栅极结构包括第一高<！ - SIPO < 介电层，P金属层，中间间隙金属层，其中中间间隙金属层形成在高金属层之间。 电介质层，P金属层和形成在P金属层上的完全硅化物层。 所述半导体系统还包括NMOS栅极结构，所述NMOS栅极结构包括第二高<！ - SIPO < 电介质层，完全硅化物层和中间间隙金属层，其中中间间隙金属层形成在高介电层之间。 电介质和完全硅化物层。
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公开(公告)号：US20090096002A1
公开(公告)日：2009-04-16
申请号：US11872546
申请日：2007-10-15
申请人： Chen-Hua Yu , Cheng-Hung Chang , Chen-Nan Yeh , Yu-Rung Hsu
发明人： Chen-Hua Yu , Cheng-Hung Chang , Chen-Nan Yeh , Yu-Rung Hsu
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/76897 , H01L23/485 , H01L29/20 , H01L29/41791 , H01L29/66795 , H01L29/7843 , H01L2029/7858
摘要： System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.
摘要翻译： 公开了用于降低接触电阻并防止由于接触不对准引起的变化的系统和方法。 优选实施例包括具有位于鳍内的源/漏区的非平面晶体管。 层间电介质覆盖非平面晶体管，并且通过层间电介质将触点形成到源/漏区。 接触件优选地与翅片的多个表面接触，以增加接触件和翅片之间的接触面积。
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17.发明授权公开(公告)号：US07518130B2
公开(公告)日：2009-04-14
申请号：US11742400
申请日：2007-04-30
IPC分类号： H01J37/317 , H01J37/08
CPC分类号： G21F1/12
摘要： An ion beam blocking component suitable for blocking an ion beam generated by an ion source of an ion implanter is provided. The blocking component includes a front plate, a back plate, and a plurality of side plates. The front plate has at least one opening. The back plate is behind the front plate, and has a plurality of grooves formed on one surface thereof facing the front plate. The side plates are connected between the front plate and the back plate, and a receiving space is formed between these plates.
摘要翻译： 提供了适合于阻挡由离子注入机的离子源产生的离子束的离子束阻挡元件。 阻挡部件包括前板，后板和多个侧板。 前板具有至少一个开口。 背板位于前板的后面，并且在其面向前板的一个表面上形成有多个槽。 侧板连接在前板和后板之间，并且在这些板之间形成容纳空间。
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公开(公告)号：US20070045568A1
公开(公告)日：2007-03-01
申请号：US11161995
申请日：2005-08-25
IPC分类号： H01J37/317 , H01J37/244
CPC分类号： H01J37/3171 , H01J37/045 , H01J2237/022 , H01J2237/24507 , H01J2237/24535
摘要： A method for reducing particles during ion implantation is provided. The method involves the use of an improved Faraday flag including a beam plate having thereon a beam striking zone comprising a recessed trench pattern on which the ion beam scans to and fro. An ion beam selected from the mass analyzer is blocked by the Faraday flag in a closed position between the mass analyzer and the semiconductor wafer. A beam current of the ion beam impinging on the beam striking zone of the beam plate is measured. After the beam current measurement, the Faraday flag is removed such that the ion beam impinges on the semiconductor wafer.
摘要翻译： 提供了离子注入期间减少颗粒的方法。 该方法包括使用改进的法拉第标志，其包括其上具有射束冲击区的梁板，该射束板包括凹陷沟槽图案，离子束在其上来回扫描。 在质量分析器和半导体晶片之间的关闭位置，选自质量分析器的离子束被法拉第标志阻挡。 测量入射在梁板的射束区上的离子束的束流。 在束电流测量之后，去除法拉第标记，使得离子束照射在半导体晶片上。
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公开(公告)号：US07160800B2
公开(公告)日：2007-01-09
申请号：US10905517
申请日：2005-01-07
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76888 , H01L21/3003 , H01L29/665
摘要： Disclosed herein are various embodiments of semiconductor devices and related methods of manufacturing a semiconductor device. In one embodiment, a method includes providing a semiconductor substrate and forming a metal silicide on the semiconductor substrate. In addition, the method includes treating an exposed surface of the metal silicide with a hydrogen/nitrogen-containing compound to form a treated layer on the exposed surface, where the composition of the treated layer hinders oxidation of the exposed surface. The method may then further include depositing a dielectric layer over the treated layer and the exposed surface of the metal silicide.
摘要翻译： 这里公开了半导体器件的各种实施例和制造半导体器件的相关方法。 在一个实施例中，一种方法包括提供半导体衬底并在半导体衬底上形成金属硅化物。 此外，该方法包括用含氢/氮化合物处理金属硅化物的暴露表面以在暴露表面上形成处理层，其中处理层的组成阻碍了暴露表面的氧化。 该方法可以进一步包括在经处理的层和金属硅化物的暴露表面上沉积介电层。
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20.发明申请Method and apparatus for real-time control and monitor of deposition processes 审中-公开用于实时控制和监测沉积过程的方法和装置公开(公告)号：US20060049036A1
公开(公告)日：2006-03-09
申请号：US10936905
申请日：2004-09-09
申请人： Cheng-Hung Chang , Jhi-Cherng Lu , Joung-Wei Liou , Chu-Yun Fu , Weng Chang , Syung-Ming Jang
发明人： Cheng-Hung Chang , Jhi-Cherng Lu , Joung-Wei Liou , Chu-Yun Fu , Weng Chang , Syung-Ming Jang
IPC分类号： C23C14/00
摘要： A method comprises measuring an RF voltage and ion current at a wafer during a plasma-enhanced deposition process, determining a sputter rate in response to the RF voltage and ion current measurements, detecting an abnormal condition in response to one of the RF voltage and ion current measurements, and sputter rate, and taking a corrective action in response to detecting an abnormal condition.
摘要翻译： 一种方法包括在等离子体增强沉积过程期间测量晶片处的RF电压和离子电流，响应于RF电压和离子电流测量确定溅射速率，响应于RF电压和离子之一检测异常状况 电流测量和溅射速率，并且响应于检测到异常状况采取校正动作。
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