公开(公告)号：US20090263970A1

公开(公告)日：2009-10-22

申请号：US12496108

申请日：2009-07-01

Applicant: Keun-Hee BAI ,  Kyeong-Koo CHI ,  Chang-Jin KANG ,  Cheol-Kyu LEE

Inventor： Keun-Hee BAI ,  Kyeong-Koo CHI ,  Chang-Jin KANG ,  Cheol-Kyu LEE

IPC: H01L21/768

CPC classification number: H01L21/0331 ,  H01L21/0332 ,  H01L21/76897

Abstract: There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.

Abstract translation: 提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。 形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，以及形成硅锗（Si1-xGex）牺牲层 ，其具有等于或高于至少导电线结构的高度的高度，在基板的整个表面上。 然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。 使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。 然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

公开(公告)号：US07329574B2

公开(公告)日：2008-02-12

申请号：US11154152

申请日：2005-06-16

Applicant: Sung-Il Cho ,  Jong-Kyu Kim ,  Byeong-Yun Nam ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee

Inventor： Sung-Il Cho ,  Jong-Kyu Kim ,  Byeong-Yun Nam ,  Kyeong-Koo Chi ,  Cheol-Kyu Lee

IPC: H01L21/8242

CPC classification number: H01L28/60 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507

Abstract: A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.

Abstract translation: 形成电容器的方法可以包括在包括氟和氧的环境中蚀刻金属氮化物层以形成电容器电极。

公开(公告)号：US20090186471A1

公开(公告)日：2009-07-23

申请号：US12321335

申请日：2009-01-20

Applicant: Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Joon-Seok Moon ,  Cheol-Kyu Lee ,  Sung-Il Cho

Inventor： Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Joon-Seok Moon ,  Cheol-Kyu Lee ,  Sung-Il Cho

IPC: H01L21/426 ,  H01L21/04

CPC classification number: H01L21/823814 ,  H01L21/823425 ,  H01L21/82385

Abstract: A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.

Abstract translation: 制造用于减少外围电路区域的杂质区域的热负荷的半导体器件的方法包括制备包括单元阵列区域中的单元有源区和外围电路区中的外围有源区的基板。 单元栅极图案和外围栅极图案可以形成在单元有源区域和外围有源区域上。 可以在电池活性区域中形成第一电池杂质区域。 可以形成第一绝缘层和牺牲绝缘层以围绕电池栅极图案和外围栅极图案。 电池导电焊盘可以形成在第一绝缘层中以电连接第一电池杂质区。 牺牲绝缘层可以与外围栅极图案相邻地去除。 第一和第二外围杂质区域可以顺序地形成在与外围栅极图案相邻的外围有源区域中。

公开(公告)号：US20090042396A1

公开(公告)日：2009-02-12

申请号：US12187895

申请日：2008-08-07

Applicant: Heung-Sik Park ,  Jun-Ho Yoon ,  Cheol-Kyu Lee ,  Joon-Soo Park

Inventor： Heung-Sik Park ,  Jun-Ho Yoon ,  Cheol-Kyu Lee ,  Joon-Soo Park

IPC: H01L21/311

CPC classification number: H01L21/3081 ,  H01L21/3065 ,  H01L29/4236 ,  H01L29/66621

Abstract: A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench.

Abstract translation: 提供一种制造半导体器件的方法。 该方法可以包括在其上限定有源区和隔离区的衬底上形成包括下硬掩模膜和上硬掩模膜的硬掩模膜，并对硬掩模膜进行构图以提供部分暴露有源区的硬掩模图案和隔离 地区。 可以使用硬掩模图案作为蚀刻掩模将蚀刻剂施加到有源和隔离区域，以在衬底的有源区域中形成沟槽，同时避免基本上蚀刻暴露于蚀刻剂的隔离区域，并且可以在栅极上形成栅极 沟。

公开(公告)号：US07226867B2

公开(公告)日：2007-06-05

申请号：US10419075

申请日：2003-04-21

Applicant: Seung-Young Son ,  Cheol-Kyu Lee ,  Chang-Jin Kang ,  Byeong-Yun Nam

Inventor： Seung-Young Son ,  Cheol-Kyu Lee ,  Chang-Jin Kang ,  Byeong-Yun Nam

IPC: H01L21/302

CPC classification number: C23F4/00 ,  H01L21/32136 ,  H01L21/32139

Abstract: Methods for etching a metal layer and a metallization method of a semiconductor device using an etching gas that includes Cl2 and N2 are provided. A mask layer is formed on the metal layer, the etching gas is supplied to the metal layer, and the metal layer is etched by the etching gas using the mask layer as an etch mask. The metal layer may be formed of aluminum or an aluminum alloy. Cl2 and N2 may be mixed at a ratio of 1:1 to 1:10. The etching gas may also include additional gases such as inactive gases or gases that include the elements H, O, F, He, or C. In addition, N2 may be supplied at a flow rate of from 45–65% of the total flow rate of the etching gas, which results in a reduction in the occurrence of micro-loading and cone-shaped defects in semiconductor devices.

Abstract translation: 提供了蚀刻金属层的方法和使用包括Cl 2 N 2和N 2 N的蚀刻气体的半导体器件的金属化方法。 在金属层上形成掩模层，将蚀刻气体供给到金属层，并使用掩模层作为蚀刻掩模，通过蚀刻气体蚀刻金属层。 金属层可以由铝或铝合金形成。 Cl 2 N 2和N 2可以1:1至1:10的比例混合。 蚀刻气体还可以包括另外的气体，例如包括元素H，O，F，He或C的惰性气体或气体。此外，N 2可以以 蚀刻气体总流量的45-65％，这导致半导体器件中的微负载和锥形缺陷的发生减少。

公开(公告)号：US07879726B2

公开(公告)日：2011-02-01

申请号：US12187895

申请日：2008-08-07

Applicant: Heung-Sik Park ,  Jun-Ho Yoon ,  Cheol-Kyu Lee ,  Joon-Soo Park

Inventor： Heung-Sik Park ,  Jun-Ho Yoon ,  Cheol-Kyu Lee ,  Joon-Soo Park

IPC: H01L21/311

CPC classification number: H01L21/3081 ,  H01L21/3065 ,  H01L29/4236 ,  H01L29/66621

Abstract: A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench.

Abstract translation: 提供一种制造半导体器件的方法。 该方法可以包括在其上限定有源区和隔离区的衬底上形成包括下硬掩模膜和上硬掩模膜的硬掩模膜，并对硬掩模膜进行构图以提供部分暴露有源区的硬掩模图案和隔离 地区。 可以使用硬掩模图案作为蚀刻掩模将蚀刻剂施加到有源和隔离区域，以在衬底的有源区域中形成沟槽，同时避免基本上蚀刻暴露于蚀刻剂的隔离区域，并且可以在栅极上形成栅极 沟。

公开(公告)号：US07879703B2

公开(公告)日：2011-02-01

申请号：US12321335

申请日：2009-01-20

Applicant: Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Joon-Seok Moon ,  Cheol-Kyu Lee ,  Sung-Il Cho

Inventor： Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Joon-Seok Moon ,  Cheol-Kyu Lee ,  Sung-Il Cho

IPC: H01L21/425

CPC classification number: H01L21/823814 ,  H01L21/823425 ,  H01L21/82385

Abstract: A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.

Abstract translation: 制造用于减少外围电路区域的杂质区域的热负荷的半导体器件的方法包括制备包括单元阵列区域中的单元有源区和外围电路区中的外围有源区的基板。 单元栅极图案和外围栅极图案可以形成在单元有源区域和外围有源区域上。 可以在电池活性区域中形成第一电池杂质区域。 可以形成第一绝缘层和牺牲绝缘层以围绕电池栅极图案和外围栅极图案。 电池导电焊盘可以形成在第一绝缘层中以电连接第一电池杂质区。 牺牲绝缘层可以与外围栅极图案相邻地去除。 第一和第二外围杂质区域可以顺序地形成在与外围栅极图案相邻的外围有源区域中。

公开(公告)号：US07763544B2

公开(公告)日：2010-07-27

申请号：US12496108

申请日：2009-07-01

Applicant: Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

Inventor： Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

IPC: H01L21/302

CPC classification number: H01L21/0331 ,  H01L21/0332 ,  H01L21/76897

Abstract: There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.

Abstract translation: 提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。 形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，以及形成硅锗（Si1-xGex）牺牲层 ，其具有等于或高于至少导电线结构的高度的高度，在基板的整个表面上。 然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。 使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。 然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

公开(公告)号：US07566659B2

公开(公告)日：2009-07-28

申请号：US11157435

申请日：2005-06-21

Applicant: Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

Inventor： Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

IPC: H01L21/44

CPC classification number: H01L21/0331 ,  H01L21/0332 ,  H01L21/76897

Abstract: There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.

Abstract translation: 提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。 形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，以及形成硅锗（Si1-xGex）牺牲层 ，其具有等于或高于至少导电线结构的高度的高度，在基板的整个表面上。 然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。 使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。 然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

公开(公告)号：US20050287738A1

公开(公告)日：2005-12-29

申请号：US11159130

申请日：2005-06-23

Applicant: Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

Inventor： Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L27/10852 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.

Abstract translation: 半导体存储器件的制造方法包括在半导体衬底上形成含碳层，在含碳层上形成绝缘层图案，将含碳层的上表面部分地露出的绝缘层图案， 蚀刻含碳层的暴露部分，形成用于限定存储节点孔的含碳层图案，在存储节点孔内部形成底部电极，在存储节点孔内部的底部电极上形成电介质层， 所述介电层覆盖所述底部电极，并且在所述存储节点孔内部的所述电介质层上形成上部电极，所述上部电极覆盖所述电介质层。