公开(公告)号：US08610191B2

公开(公告)日：2013-12-17

申请号：US12958601

申请日：2010-12-02

申请人： Joon-Seok Moon ,  Dong-Soo Woo ,  Jaerok Kahng ,  Jinwoo Lee ,  Keeshik Park

发明人： Joon-Seok Moon ,  Dong-Soo Woo ,  Jaerok Kahng ,  Jinwoo Lee ,  Keeshik Park

IPC分类号： H01L29/78 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L29/4236

摘要： Semiconductor devices and dynamic random access memory devices including a buried gate electrode are provided, the semiconductor devices include a substrate with a gate trench, a buried gate electrode partially filling the inside of the gate trench, a capping layer pattern in the gate trench and over the buried gate electrode, source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode, and a gate insulation layer interposed between the trench and the buried gate electrode. The capping layer pattern includes a high-k material layer that directly contacts an upper surface of the buried gate electrode.

摘要翻译： 提供了包括掩埋栅电极的半导体器件和动态随机存取存储器件，半导体器件包括具有栅极沟槽的衬底，部分填充栅极沟槽内部的掩埋栅电极，栅极沟槽中的覆盖层图案 掩埋栅电极，在衬底的上表面下方并且与掩埋栅电极的两侧相邻的源极/漏极区以及介于沟槽和掩埋栅极之间的栅极绝缘层。 覆盖层图案包括直接接触掩埋栅电极的上表面的高k材料层。

公开(公告)号：US08426274B2

公开(公告)日：2013-04-23

申请号：US12861247

申请日：2010-08-23

申请人： Jun-Ho Yoon ,  Kyoung-Sub Shin ,  Sung-Sam Lee ,  Kung-Hyon Nam ,  Hong Cho ,  Joon-Seok Moon

发明人： Jun-Ho Yoon ,  Kyoung-Sub Shin ,  Sung-Sam Lee ,  Kung-Hyon Nam ,  Hong Cho ,  Joon-Seok Moon

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/02238 ,  H01L21/3065 ,  H01L29/66621

摘要： Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.

摘要翻译： 示例性实施例涉及形成凹部的方法和制造具有该凹部的半导体器件的方法。 该方法包括形成在衬底中限定有源区的场区域。 有源区在衬底中沿第一方向延伸。 所述方法还包括形成在与所述第一方向不同的第二方向上延伸并且与所述衬底中的有源区交叉的预备凹槽，等离子体氧化所述衬底以沿着具有所述初步凹槽的所述衬底的表面形成牺牲氧化物层，以及 通过等离子体蚀刻去除牺牲氧化物层和有源区的部分以形成具有大于初步凹槽的宽度的宽度的凹部，其中有源区的蚀刻速率是其中的蚀刻速率的一到两倍 牺牲氧化层。

公开(公告)号：US08035136B2

公开(公告)日：2011-10-11

申请号：US12508305

申请日：2009-07-23

申请人： Sung-Sam Lee ,  Joon-Seok Moon ,  Young-Ju Choi

发明人： Sung-Sam Lee ,  Joon-Seok Moon ,  Young-Ju Choi

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L28/91 ,  H01L21/823437 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L28/65

摘要： In a semiconductor device and a method of manufacturing the same, a substrate is defined into active and non-active regions by a device isolation layer and a recessed portion is formed on the active region. A gate electrode includes a gate insulation layer on an inner sidewall and a bottom of the recessed portion, a lower electrode on the gate insulation layer and an inner spacer on the lower electrode in the recessed portion, and an upper electrode that is positioned on the inner spacer and connected to the lower electrode. Source and drain impurity regions are formed at surface portions of the active region of the substrate adjacent to the upper electrode. Accordingly, the source and drain impurity regions are electrically insulated by the inner spacer in the recessed portion of the substrate like a bridge, to thereby sufficiently prevent gate-induced drain leakage (GIDL) at the gate electrode.

摘要翻译： 在半导体器件及其制造方法中，通过器件隔离层将衬底限定为有源区域和非有源区域，并且在有源区域上形成凹部。 栅极电极包括在内侧壁和凹部的底部上的栅极绝缘层，栅极绝缘层上的下部电极和凹部中的下部电极上的内部间隔物，以及位于 内部间隔件并连接到下部电极。 源极和漏极杂质区形成在与上电极相邻的衬底的有源区的表面部分处。 因此，源极和漏极杂质区域如桥接在衬底的凹陷部分中的内部间隔物电绝缘，从而充分防止栅电极处的栅极引起的漏极泄漏（GIDL）。

公开(公告)号：US20110169066A1

公开(公告)日：2011-07-14

申请号：US12958601

申请日：2010-12-02

申请人： Joon-Seok MOON ,  Dong-Soo WOO ,  Jaerok KAHNG ,  Jinwoo LEE ,  Keeshik PARK

发明人： Joon-Seok MOON ,  Dong-Soo WOO ,  Jaerok KAHNG ,  Jinwoo LEE ,  Keeshik PARK

IPC分类号： H01L29/78 ,  H01L27/108

CPC分类号： H01L27/10876 ,  H01L29/4236

摘要： Semiconductor devices and dynamic random access memory devices including a buried gate electrode are provided, the semiconductor devices include a substrate with a gate trench, a buried gate electrode partially filling the inside of the gate trench, a capping layer pattern in the gate trench and over the buried gate electrode, source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode, and a gate insulation layer interposed between the trench and the buried gate electrode. The capping layer pattern includes a high-k material layer that directly contacts an upper surface of the buried gate electrode.

摘要翻译： 提供了包括掩埋栅电极的半导体器件和动态随机存取存储器件，半导体器件包括具有栅极沟槽的衬底，部分填充栅极沟槽内部的掩埋栅电极，栅极沟槽中的覆盖层图案 掩埋栅电极，在衬底的上表面下方并且与掩埋栅电极的两侧相邻的源极/漏极区以及介于沟槽和掩埋栅极之间的栅极绝缘层。 覆盖层图案包括直接接触掩埋栅电极的上表面的高k材料层。

公开(公告)号：US20110001934A1

公开(公告)日：2011-01-06

申请号：US12707912

申请日：2010-02-18

申请人： Seok-chan HONG ,  Won-yong LEE ,  Joon-seok MOON

发明人： Seok-chan HONG ,  Won-yong LEE ,  Joon-seok MOON

IPC分类号： G03B21/14 ,  F21V9/14

CPC分类号： G02B27/0961 ,  G02B27/285 ,  G03B21/2073 ,  G03B21/208 ,  H04N9/3152 ,  H04N9/3167

摘要： An illumination optical unit and a display apparatus having the same are provided. The display apparatus includes an illumination optical unit which generates and illuminates light; a display element which forms an image by the light illuminated from the illumination optical unit; and a projection optical unit which projects the image formed in the display element on a screen. The illumination optical unit includes a light source which includes a light emitting area, and a polarization converting unit which includes a plurality of polarization prisms which polarize and convert an entering light from the light source. The light source is disposed so that a long width of the light emitting area corresponds to a long width of the polarization prisms.

摘要翻译： 提供一种照明光学单元及具有该照明光学单元的显示装置。 显示装置包括产生并照亮光的照明光学单元; 通过从照明光学单元照射的光形成图像的显示元件; 以及将形成在显示元件上的图像投影在屏幕上的投影光学单元。 照明光学单元包括包括发光区域的光源和包括使来自光源的入射光偏振并转换的多个偏振棱镜的偏振转换单元。 光源被设置为使得发光区域的长宽度对应于偏振棱镜的长宽度。

公开(公告)号：US20060285081A1

公开(公告)日：2006-12-21

申请号：US11336789

申请日：2006-01-23

申请人： Joon-seok Moon ,  Sang-il Park ,  Alexel Borodouline

发明人： Joon-seok Moon ,  Sang-il Park ,  Alexel Borodouline

IPC分类号： G03B21/28

CPC分类号： G03B21/28

摘要： A portable rear projection apparatus includes a lens element for magnifying an image projected from a projector, an aspherical mirror for reflecting the image magnified by the lens element to change a light path, a screen for displaying the image reflected from the aspherical mirror, and a movable screen support for supporting the screen.

摘要翻译： 便携式背投装置包括用于放大从投影仪投影的图像的透镜元件，用于反射由透镜元件放大的图像以改变光路的非球面镜，用于显示从非球面镜反射的图像的屏幕，以及 可移动屏幕支持支持屏幕。

公开(公告)号：US20130043519A1

公开(公告)日：2013-02-21

申请号：US13589339

申请日：2012-08-20

申请人： Joon-seok Moon ,  Jae-rok Kahng ,  Jin-woo Lee ,  Sung-sam Lee ,  Dong-soo Woo ,  Kyoung-ho Jung ,  Jung-kyu Jung

发明人： Joon-seok Moon ,  Jae-rok Kahng ,  Jin-woo Lee ,  Sung-sam Lee ,  Dong-soo Woo ,  Kyoung-ho Jung ,  Jung-kyu Jung

IPC分类号： H01L29/78

CPC分类号： H01L29/4236 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/42368

摘要： A device includes a semiconductor substrate and a gate insulation film lining a trench in an active region of the substrate. A gate electrode pattern is recessed in the trench on the gate insulation film and has an upper surface that has a nonuniform height. A dielectric pattern may be disposed on the gate electrode pattern in the trench.

摘要翻译： 一种器件包括半导体衬底和衬在衬底的有源区中的沟槽的栅极绝缘膜。 栅极电极图案凹陷在栅极绝缘膜上的沟槽中，并且具有不均匀高度的上表面。 电介质图案可以设置在沟槽中的栅电极图案上。

公开(公告)号：US20110053327A1

公开(公告)日：2011-03-03

申请号：US12861247

申请日：2010-08-23

申请人： Jun-Ho YOON ,  Kyoung-Sub Shin ,  Sung-Sam Lee ,  Kung-Hyon Nam ,  Hong Cho ,  Joon-Seok Moon

发明人： Jun-Ho YOON ,  Kyoung-Sub Shin ,  Sung-Sam Lee ,  Kung-Hyon Nam ,  Hong Cho ,  Joon-Seok Moon

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/02238 ,  H01L21/3065 ,  H01L29/66621

摘要： Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.

摘要翻译： 示例性实施例涉及形成凹部的方法和制造具有该凹部的半导体器件的方法。 该方法包括形成在衬底中限定有源区的场区域。 有源区域在衬底中沿第一方向延伸。 所述方法还包括形成在与所述第一方向不同的第二方向上延伸并且与所述衬底中的有源区交叉的预备凹槽，等离子体氧化所述衬底以沿着具有所述初步凹槽的所述衬底的表面形成牺牲氧化物层，以及 通过等离子体蚀刻去除牺牲氧化物层和有源区的部分以形成具有大于初步凹槽的宽度的宽度的凹部，其中有源区的蚀刻速率是其中的蚀刻速率的一到两倍 牺牲氧化层。

公开(公告)号：US20100019302A1

公开(公告)日：2010-01-28

申请号：US12508305

申请日：2009-07-23

申请人： Sung-Sam Lee ,  Joon-Seok Moon ,  Young-Ju Choi

发明人： Sung-Sam Lee ,  Joon-Seok Moon ,  Young-Ju Choi

IPC分类号： H01L27/10 ,  H01L21/8234 ,  H01L21/02

CPC分类号： H01L28/91 ,  H01L21/823437 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L28/65

摘要： In a semiconductor device and a method of manufacturing the same, a substrate is defined into active and non-active regions by a device isolation layer and a recessed portion is formed on the active region. A gate electrode includes a gate insulation layer on an inner sidewall and a bottom of the recessed portion, a lower electrode on the gate insulation layer and an inner spacer on the lower electrode in the recessed portion, and an upper electrode that is positioned on the inner spacer and connected to the lower electrode. Source and drain impurity regions are formed at surface portions of the active region of the substrate adjacent to the upper electrode. Accordingly, the source and drain impurity regions are electrically insulated by the inner spacer in the recessed portion of the substrate like a bridge, to thereby sufficiently prevent gate-induced drain leakage (GIDL) at the gate electrode.

摘要翻译： 在半导体器件及其制造方法中，通过器件隔离层将衬底限定为有源区域和非有源区域，并且在有源区域上形成凹部。 栅极电极包括在内侧壁和凹部的底部上的栅极绝缘层，栅极绝缘层上的下部电极和凹部中的下部电极上的内部间隔物，以及位于 内部间隔件并连接到下部电极。 源极和漏极杂质区形成在与上电极相邻的衬底的有源区的表面部分处。 因此，源极和漏极杂质区域如桥接在衬底的凹陷部分中的内部间隔物电绝缘，从而充分防止栅电极处的栅极引起的漏极泄漏（GIDL）。

公开(公告)号：US07879703B2

公开(公告)日：2011-02-01

申请号：US12321335

申请日：2009-01-20

申请人： Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Joon-Seok Moon ,  Cheol-Kyu Lee ,  Sung-Il Cho

发明人： Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Joon-Seok Moon ,  Cheol-Kyu Lee ,  Sung-Il Cho

IPC分类号： H01L21/425

CPC分类号： H01L21/823814 ,  H01L21/823425 ,  H01L21/82385

摘要： A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.

摘要翻译： 制造用于减少外围电路区域的杂质区域的热负荷的半导体器件的方法包括制备包括单元阵列区域中的单元有源区和外围电路区中的外围有源区的基板。 单元栅极图案和外围栅极图案可以形成在单元有源区域和外围有源区域上。 可以在电池活性区域中形成第一电池杂质区域。 可以形成第一绝缘层和牺牲绝缘层以围绕电池栅极图案和外围栅极图案。 电池导电焊盘可以形成在第一绝缘层中以电连接第一电池杂质区。 牺牲绝缘层可以与外围栅极图案相邻地去除。 第一和第二外围杂质区域可以顺序地形成在与外围栅极图案相邻的外围有源区域中。