公开(公告)号：US20130099838A1

公开(公告)日：2013-04-25

申请号：US13334241

申请日：2011-12-22

Applicant: Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

Inventor： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

IPC: H03L7/095

CPC classification number: H03L7/0814 ,  G11C7/222 ,  G11C11/40 ,  G11C29/023 ,  G11C2029/0409

Abstract: A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

Abstract translation: 半导体集成电路包括：延迟锁定环（DLL），被配置为通过将源时钟信号延迟第一延迟时间来获得锁定来产生DLL时钟信号，其中响应于更新来控制DLL的更新周期 锁定后的周期控制信号完成; 以及更新周期控制器，被配置为响应于源时钟信号和从DLL提供的多个控制信号，基于在DLL的循环路径中出现的第二延迟时间来生成更新周期控制信号。

公开(公告)号：US08283962B2

公开(公告)日：2012-10-09

申请号：US12005515

申请日：2007-12-27

Applicant: Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

Inventor： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC: H03K3/00

CPC classification number: G06F1/06

Abstract: A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.

Abstract translation: 半导体存储器件可以基于多相时钟信号来优化布局面积和电流消耗，该多相时钟信号是通过使用没有延迟锁定环路和锁相环路的复位信号对源时钟信号进行分频而产生的，以便具有 低频和不同的激活时序具有恒定的相位差。

公开(公告)号：US08130890B2

公开(公告)日：2012-03-06

申请号：US12005492

申请日：2007-12-27

Applicant: Kyung-Hoon Kim ,  Yong-Ki Kim ,  Dae-Han Kwon ,  Taek-Sang Song

Inventor： Kyung-Hoon Kim ,  Yong-Ki Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC: H04L7/02 ,  H04L7/04

CPC classification number: G11C29/02 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028

Abstract: A data clock frequency divider circuit includes a training decoder and a frequency divider. The training decoder outputs a clock alignment training signal, which is indicative of the start of a clock alignment training, in response to a command and an address of a mode register set. The frequency divider, which is reset in response to an output of the training decoder, receives an internal data clock to divide a frequency of the internal data clock in half. The data clock frequency divider circuit secures a sufficient operating margin so that a data clock and a system clock are aligned within a pre-set clock training operation time by resetting the data clock to correspond to a timing in which the clock training operation starts, thereby providing a clock training for a high-speed system.

Abstract translation: 数据时钟分频器电路包括训练解码器和分频器。 响应于模式寄存器组的命令和地址，训练解码器输出表示时钟对准训练的开始的时钟对准训练信号。 响应于训练解码器的输出复位的分频器接收内部数据时钟以将内部数据时钟的频率分成两半。 数据时钟分频器电路确保足够的操作余量，使得数据时钟和系统时钟在预设的时钟训练操作时间内对齐，通过复位数据时钟以对应于时钟训练操作开始的定时，由此 为高速系统提供时钟训练。

公开(公告)号：US08130034B2

公开(公告)日：2012-03-06

申请号：US12833154

申请日：2010-07-09

Applicant: Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

Inventor： Taek-Sang Song ,  Dae-Han Kwon ,  Jun-Woo Lee

IPC: H03F3/45

CPC classification number: H03F3/45192

Abstract: A rail-to-rail amplifier includes an NMOS type amplification unit configured to perform an amplification operation on differential input signals in a domain in which DC levels of the differential input signals are higher than a first threshold value, a PMOS type folded-cascode amplification unit configured to perform an amplification operation on the differential input signals in a domain in which the DC levels of the differential input signals are lower than a second threshold value which is higher than the first threshold value, the PMOS type folded-cascode amplification unit being cascade-coupled to the NMOS type amplification unit, and an adaptive biasing unit configured to interrupt a current path of the PMOS type folded-cascode amplification unit in a domain in which the DC levels of the differential input signals are higher than the second threshold value in response to the differential input signals.

Abstract translation: 轨到轨放大器包括：NMOS型放大单元，被配置为对差分输入信号的DC电平高于第一阈值的区域中的差分输入信号进行放大操作，PMOS型折叠共源共栅放大 被配置为对差分输入信号的DC电平低于高于第一阈值的第二阈值的区域中的差分输入信号进行放大操作的单元，PMOS型折叠共源共栅放大单元是 级联耦合到NMOS型放大单元，以及自适应偏置单元，被配置为在差分输入信号的DC电平高于第二阈值的区域中断PMOS型折叠共源共栅放大单元的电流路径 响应于差分输入信号。

公开(公告)号：US20110140768A1

公开(公告)日：2011-06-16

申请号：US12647875

申请日：2009-12-28

Applicant: Taek-Sang SONG ,  Dae-Han KWON ,  Jun-Woo LEE

Inventor： Taek-Sang SONG ,  Dae-Han KWON ,  Jun-Woo LEE

IPC: G05F1/10

CPC classification number: G05F1/56

Abstract: An internal voltage generator includes: a detection unit configured to detect a level of an internal voltage in comparison to a reference voltage; a first driving unit configured to discharge an internal voltage terminal, through which the internal voltage is outputted, in response to an output signal of the detection unit; a current detection unit configured to detect a discharge current flowing through the first driving unit; and a second driving unit configured to charge the internal voltage terminal in response to an output signal of the current detection unit.

Abstract translation: 内部电压发生器包括：检测单元，被配置为与参考电压相比检测内部电压的电平; 第一驱动单元，被配置为响应于所述检测单元的输出信号，对输出所述内部电压的内部电压端子进行放电; 电流检测单元，被配置为检测流过所述第一驱动单元的放电电流; 以及第二驱动单元，其被配置为响应于所述电流检测单元的输出信号对所述内部电压端子进行充电。

公开(公告)号：US07952438B2

公开(公告)日：2011-05-31

申请号：US12217049

申请日：2008-06-30

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC: H03B27/01

CPC classification number: H03L7/0812 ,  H03L7/18 ,  H03L7/24

Abstract: An injection locking clock generator can vary the free running frequency of an injection locking oscillator to broaden an operating frequency range of an oscillation signal injected to itself, thereby performing an injection locking with respect to all frequencies of an operating frequency range. The clock generator includes a main oscillator configured to generate oscillation signals of a frequency corresponding to a control voltage, and an injection locking oscillator configured to generate division signals synchronized with the oscillation signals by dividing the oscillation signals, wherein a free running frequency of the injection locking oscillator is set according to the frequency of the oscillation signals.

Abstract translation: 注入锁定时钟发生器可以改变注入锁定振荡器的自由运行频率，以扩大注入到其自身的振荡信号的工作频率范围，从而相对于工作频率范围的所有频率执行注入锁定。 时钟发生器包括：主振荡器，其被配置为产生与控制电压对应的频率的振荡信号;以及注入锁定振荡器，其被配置为通过划分所述振荡信号产生与所述振荡信号同步的除法信号，其中所述注入的自由运行频率 锁定振荡器根据振荡信号的频率设定。

公开(公告)号：US07948814B2

公开(公告)日：2011-05-24

申请号：US12164797

申请日：2008-06-30

Applicant: Dae-Han Kwon ,  Kyung-Hoon Kim ,  Taek-Sang Song

Inventor： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Taek-Sang Song

IPC: G11C7/00

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C7/225

Abstract: A semiconductor memory device including a clock input for receiving a source clock and supplying a generated clock to a plurality of clock transmission lines; a plurality of clock amplifiers, each amplifying a respective generated clock loaded on one of the plurality of clock transmission lines in response to a column enable signal; and a data input/output for inputting/outputting a plurality of data in response to the amplified clocks output by the plurality of clock amplifiers.

Abstract translation: 一种半导体存储器件，包括用于接收源时钟并将产生的时钟提供给多个时钟传输线的时钟输入; 多个时钟放大器，每个时钟放大器响应于列使能信号放大加载在所述多个时钟传输线中的一个上的相应的生成时钟; 以及用于响应于由多个时钟放大器输出的放大时钟而输入/输出多个数据的数据输入/输出。

公开(公告)号：US07881129B2

公开(公告)日：2011-02-01

申请号：US12010247

申请日：2008-01-23

Applicant: Sang-kug Park ,  Dae-han Kim

Inventor： Sang-kug Park ,  Dae-han Kim

IPC: G11C5/14

CPC classification number: G11C16/12 ,  G11C5/145 ,  G11C11/5628 ,  G11C16/30 ,  G11C16/3454

Abstract: A high voltage regulator may include a first regulating unit, a second regulating unit, and an output node. The first regulating unit regulates the program voltage in a voltage-level-up interval of a program voltage of a memory cell. The second regulating unit regulates the program voltage in a voltage-level-down interval of the program voltage. The output node outputs the regulated program voltage.

Abstract translation: 高压调节器可以包括第一调节单元，第二调节单元和输出节点。 第一调节单元在存储器单元的编程电压的电压升高间隔中调节编程电压。 第二调节单元在编程电压的电压降低间隔中调节编程电压。 输出节点输出调节编程电压。

公开(公告)号：US07863955B2

公开(公告)日：2011-01-04

申请号：US12005564

申请日：2007-12-27

Applicant: Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

Inventor： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC: H03K3/017

CPC classification number: H03K5/1565

Abstract: A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to frequencies of external clock signals, and a duty ratio detecting unit for detecting a duty ratio of the external clock signals in response to the enable signal.

Abstract translation: 一种半导体器件包括：脉冲信号产生单元，用于产生彼此具有不同脉冲宽度的多个脉冲信号;信号复用单元，用于响应于频率输出多个脉冲信号中的一个作为使能信号 以及占空比检测单元，用于响应于使能信号检测外部时钟信号的占空比。

公开(公告)号：US07768307B2

公开(公告)日：2010-08-03

申请号：US12005443

申请日：2007-12-26

Applicant: Kyung-Hoon Kim ,  Dae-Han Kwon

Inventor： Kyung-Hoon Kim ,  Dae-Han Kwon

IPC: H03K19/0175

CPC classification number: H03K19/018521 ,  H03K19/0948

Abstract: A current mode logic (CML)-complementary metal oxide semiconductor (CMOS) converter prevents change of a duty ratio to stably operate during an operation for converting a CML level signal into a CMOS level signal. The CML-CMOS converter includes a reference level shifting unit configured to receive a CML signal swinging about a first reference level to shift a swing reference level to a second reference level; and an amplifying unit configured to amplify an output signal of the reference level shifting unit to output the amplified signal as a CMOS signal.

Abstract translation: 电流模式逻辑（CML） - 互补金属氧化物半导体（CMOS）转换器在用于将CML电平信号转换为CMOS电平信号的操作期间防止占空比的变化以稳定地操作。 CML-CMOS转换器包括参考电平移位单元，被配置为接收围绕第一参考电平摆动的CML信号，以将摆幅参考电平移位到第二参考电平; 以及放大单元，被配置为放大参考电平移位单元的输出信号以输出放大的信号作为CMOS信号。