公开(公告)号：US08542044B2

公开(公告)日：2013-09-24

申请号：US13334241

申请日：2011-12-22

申请人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

发明人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G11C7/222 ,  G11C11/40 ,  G11C29/023 ,  G11C2029/0409

摘要： A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

摘要翻译： 半导体集成电路包括：延迟锁定环（DLL），被配置为通过将源时钟信号延迟第一延迟时间来获得锁定来产生DLL时钟信号，其中响应于更新来控制DLL的更新周期 锁定后的周期控制信号完成; 以及更新周期控制器，被配置为响应于源时钟信号和从DLL提供的多个控制信号，基于在DLL的循环路径中出现的第二延迟时间来生成更新周期控制信号。

公开(公告)号：US08633762B2

公开(公告)日：2014-01-21

申请号：US13333692

申请日：2011-12-21

申请人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

发明人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

IPC分类号： H01L25/00

CPC分类号： G06F13/4077

摘要： A system for transmitting data includes a plurality of data lines configured to transmit the data and a transmitting chip configured to output the data to the data lines and perform a crosstalk prevention operation in response to a data pattern of the data to be transmitted through the data lines and array information of the data lines to prevent crosstalk from occurring in the data lines.

摘要翻译： 用于发送数据的系统包括被配置为发送数据的多条数据线和被配置为将数据输出到数据线的发送芯片，并且响应于要通过数据发送的数据的数据模式执行串扰防止操作 数据线的线和阵列信息，以防止在数据线中发生串扰。

公开(公告)号：US20130099838A1

公开(公告)日：2013-04-25

申请号：US13334241

申请日：2011-12-22

申请人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

发明人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

IPC分类号： H03L7/095

CPC分类号： H03L7/0814 ,  G11C7/222 ,  G11C11/40 ,  G11C29/023 ,  G11C2029/0409

摘要： A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

摘要翻译： 半导体集成电路包括：延迟锁定环（DLL），被配置为通过将源时钟信号延迟第一延迟时间来获得锁定来产生DLL时钟信号，其中响应于更新来控制DLL的更新周期 锁定后的周期控制信号完成; 以及更新周期控制器，被配置为响应于源时钟信号和从DLL提供的多个控制信号，基于在DLL的循环路径中出现的第二延迟时间来生成更新周期控制信号。

公开(公告)号：US20130051491A1

公开(公告)日：2013-02-28

申请号：US13333692

申请日：2011-12-21

申请人： Yong-Ju KIM ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

发明人： Yong-Ju KIM ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

IPC分类号： H04L25/49

CPC分类号： G06F13/4077

摘要： A system for transmitting data includes a plurality of data lines configured to transmit the data and a transmitting chip configured to output the data to the data lines and perform a crosstalk prevention operation in response to a data pattern of the data to be transmitted through the data lines and array information of the data lines to prevent crosstalk from occurring in the data lines.

摘要翻译： 用于发送数据的系统包括被配置为发送数据的多条数据线和被配置为将数据输出到数据线的发送芯片，并且响应于要通过数据发送的数据的数据模式执行串扰防止操作 数据线的线和阵列信息，以防止在数据线中发生串扰。

公开(公告)号：US08867698B2

公开(公告)日：2014-10-21

申请号：US13620564

申请日：2012-09-14

申请人： Dae-Han Kwon ,  Yong-Ju Kim ,  Jae-Il Kim ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Yong-Ju Kim ,  Jae-Il Kim ,  Taek-Sang Song

IPC分类号： H03K21/38

CPC分类号： H03K21/38 ,  H03K21/023

摘要： A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.

摘要翻译： 计数电路包括：时钟分割单元，被配置为以预设的分频比划分参考时钟信号并产生分频时钟信号;计数单元，被配置为对分频时钟信号进行计数;计数控制单元，被配置为使计数单元 在对应于分频比的使能期间。

公开(公告)号：US08664987B2

公开(公告)日：2014-03-04

申请号：US13607234

申请日：2012-09-07

申请人： Dae-Han Kwon ,  Yong-Ju Kim ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Yong-Ju Kim ,  Taek-Sang Song

IPC分类号： H03K5/00

CPC分类号： H03L7/093 ,  H03L7/0812 ,  H03L7/235

摘要： A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

摘要翻译： 滤波电路包括时钟选择单元，其被配置为响应于频率信号将具有低于第一时钟的频率的第一时钟或第二时钟作为工作时钟传送;以及滤波器，被配置为对输入信号进行滤波并生成滤波的 信号与操作时钟同步。

公开(公告)号：US20120262323A1

公开(公告)日：2012-10-18

申请号：US13333983

申请日：2011-12-21

申请人： Taek-Sang SONG ,  Dae-Han Kwon

发明人： Taek-Sang SONG ,  Dae-Han Kwon

IPC分类号： H04L17/02

CPC分类号： H03K5/2481 ,  H03K19/0027 ,  H03K19/0948

摘要： A buffer control circuit includes a current supply unit configured to supply current and adjust the current in response to codes, an amplifying buffer configured to operate using the current and output a value obtained by comparing a reference potential and the reference potential, a second buffer configured to buffer an output of the first buffer, and a code generation unit configured to generate the codes in response to an output of the second buffer.

摘要翻译： 缓冲器控制电路包括：电流供给单元，被配置为响应于代码提供电流并调节电流;放大缓冲器，被配置为使用电流进行操作并输出通过比较参考电位和参考电位获得的值;配置的第二缓冲器 以缓冲第一缓冲器的输出;以及代码生成单元，被配置为响应于第二缓冲器的输出而生成代码。

公开(公告)号：US08253465B2

公开(公告)日：2012-08-28

申请号：US13186366

申请日：2011-07-19

申请人： Dae-Kun Yoon ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Dae-Kun Yoon ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H03K3/00 ,  H03K5/13 ,  H03H11/16

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0814

摘要： A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.

摘要翻译： 半导体存储器件包括边缘检测器，被配置为接收两对互补时钟以检测时钟的边沿;比较器，被配置为比较边缘检测器的输出信号，以检测同一对的时钟是否具有180度的相位差;以及 检测不同对的时钟是否具有90度的相位差，控制信号发生器被配置为根据比较器的输出信号产生用于控制时钟相位的控制信号;以及相位校正器，被配置为校正时钟的相位 响应于控制信号。

公开(公告)号：US07986161B2

公开(公告)日：2011-07-26

申请号：US12327294

申请日：2008-12-03

申请人： Jun-Woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Jun-Woo Lee ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H03K17/16

CPC分类号： H03K19/018585 ,  H04L25/0298

摘要： A termination resistance circuit includes a control signal generator for generating a control signal whose logical value changes when a calibration code has a predetermined value, a plurality of parallel resistors which are respectively turned on/off in response to the calibration code, and a resistance value changing unit for changing the total resistance value of the termination resistance circuit in response to the control signal.

摘要翻译： 终端电阻电路包括控制信号发生器，用于产生当校准码具有预定值时其逻辑值改变的控制信号，响应于校准码分别导通/关断的多个并联电阻器，以及电阻值 改变单元，用于响应于控制信号改变终端电阻电路的总电阻值。

公开(公告)号：US07961026B2

公开(公告)日：2011-06-14

申请号：US12003676

申请日：2007-12-31

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03H11/26

CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03L2207/06

摘要： A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

摘要翻译： 通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环，从而提高内部时钟的抖动特性。 延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器，以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。 锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器，用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器 响应于控制电压和一个或多个频率范围控制信号，其中使用内部时钟产生反馈时钟。