公开(公告)号：US09257444B2

公开(公告)日：2016-02-09

申请号：US14018578

申请日：2013-09-05

申请人： Jung-Ik Oh ,  Dae-Hyun Jang ,  Kyoung-Sub Shin

发明人： Jung-Ik Oh ,  Dae-Hyun Jang ,  Kyoung-Sub Shin

IPC分类号： H01L21/336 ,  H01L27/115

CPC分类号： H01L27/11565 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, dummy area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.

公开(公告)号：US20100033626A1

公开(公告)日：2010-02-11

申请号：US12411917

申请日：2009-03-26

申请人： Dae-hyun Jang ,  Oh-yun Kwon ,  Young-joong Noh

发明人： Dae-hyun Jang ,  Oh-yun Kwon ,  Young-joong Noh

IPC分类号： H04N7/04

CPC分类号： H04N5/145 ,  H04N5/44543 ,  H04N7/0115 ,  H04N7/013 ,  H04N19/132 ,  H04N19/139 ,  H04N19/142 ,  H04N19/44 ,  H04N19/51 ,  H04N19/587 ,  H04N21/4104 ,  H04N21/42607 ,  H04N21/488

摘要： Disclosed is a control method of an image processing apparatus, the control method including: processing one among a first image, a second image formed on the basis of a different frame rate from that of the first image, and an overlay image where the first image is overlapped with the second image, which is inputted, to be displayable; and compensating for a motion of the processed image on the basis of the first image if it is determined that the inputted image is the first image or the overlay image.

摘要翻译： 公开了一种图像处理装置的控制方法，所述控制方法包括：处理第一图像，基于与第一图像的帧速率不同的帧速率形成的第二图像之一，以及第一图像 重叠在第二图像，其被输入时，为可显示; 并补偿所述第一图像的基础上，处理后的图像的运动，如果确定所输入的图像是所述第一图像或所述覆盖图像。

公开(公告)号：US07615496B2

公开(公告)日：2009-11-10

申请号：US11589798

申请日：2006-10-31

申请人： Ji-young Lee ,  Dae-hyun Jang

发明人： Ji-young Lee ,  Dae-hyun Jang

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76838 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/105 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A self-align patterning method for forming patterns includes forming a first layer on a substrate, forming a plurality of first hard mask patterns on the first layer, forming a sacrificial layer on top surfaces and sidewalls of the first hard mask patterns, thereby forming a gap between respective facing portions of the sacrificial layer on the sidewalls of the first hard mask patterns, forming a second hard mask pattern in the gap, etching the sacrificial layer using the second hard mask pattern as a mask to expose the first hard mask patterns, exposing the first layer using the exposed first hard mask patterns and the second hard mask pattern, and etching the exposed first layer using the first and second hard mask patterns.

摘要翻译： 用于形成图案的自对准图案化方法包括在衬底上形成第一层，在第一层上形成多个第一硬掩模图案，在第一硬掩模图案的顶表面和侧壁上形成牺牲层，由此形成 在第一硬掩模图案的侧壁上的牺牲层的相对面对部分之间的间隙，在间隙中形成第二硬掩模图案，使用第二硬掩模图案作为掩模蚀刻牺牲层以暴露第一硬掩模图案， 使用暴露的第一硬掩模图案和第二硬掩模图案曝光第一层，并且使用第一和第二硬掩模图案蚀刻暴露的第一层。

公开(公告)号：US20090228793A1

公开(公告)日：2009-09-10

申请号：US12337085

申请日：2008-12-17

申请人： Young-joong NOH ,  Woo-jung KIM ,  Dae-hyun JANG

发明人： Young-joong NOH ,  Woo-jung KIM ,  Dae-hyun JANG

IPC分类号： G06F3/048

CPC分类号： G04G9/0076

摘要： A display apparatus includes a display unit, a storage unit which stores a zone name and standard time information corresponding to the zone name, a user interface (UI) generator which generates a time information image, and a controller which receives local real-time information from an external source, calculates a time corresponding to a selected zone based on the local real-time information and the standard time information, and controls the UI generator to generate the time information image containing the calculated time to be displayed on the display unit.

摘要翻译： 显示装置包括显示单元，存储区域名称和对应于区域名称的标准时间信息的存储单元，产生时间信息图像的用户接口（UI）生成器以及接收本地实时信息的控制器 根据本地实时信息和标准时间信息，从外部源计算与所选择的区域对应的时间，并且控制UI生成器以生成包含要在显示单元上显示的计算出的时间的时间信息图像。

公开(公告)号：US20080316160A1

公开(公告)日：2008-12-25

申请号：US12142398

申请日：2008-06-19

申请人： Dae-Hyun Jang ,  Hun Jeoung

发明人： Dae-Hyun Jang ,  Hun Jeoung

IPC分类号： G09G3/36

CPC分类号： G09G3/3655 ,  G09G2320/02

摘要： A common voltage driving circuit of a liquid crystal display, includes: a clock signal input unit that comprises a plurality of transistors and inputs first and second clock signals according to a gate output voltage; an output node voltage controller that comprises a plurality of transistors and condensers and changes voltages of positive and negative polarity output nodes by the first and second clock signals and first to third gate output voltages; an initialization voltage supply unit that comprises a plurality of transistors and supplies an initialization voltage of the output node voltage controller; and a common voltage output unit that comprises a plurality of transistors and a single condenser and prevents the voltages of the positive and negative polarity output nodes from being changed by using the condenser in alternately outputting higher and lower common voltages according to the voltages of the positive and negative polarity output nodes.

摘要翻译： 一种液晶显示器的公共电压驱动电路，包括：时钟信号输入单元，包括多个晶体管，并根据栅极输出电压输入第一和第二时钟信号; 输出节点电压控制器，其包括多个晶体管和电容器，并且通过第一和第二时钟信号以及第一至第三栅极输出电压改变正极性和负极性输出节点的电压; 初始化电压提供单元，其包括多个晶体管，并提供所述输出节点电压控制器的初始化电压; 以及公共电压输出单元，其包括多个晶体管和单个电容器，并且通过使用电容器根据正的电压交替地输出较高和较低的公共电压来防止正极性和负极性输出节点的电压被改变 和负极性输出节点。

公开(公告)号：US09543307B2

公开(公告)日：2017-01-10

申请号：US14792114

申请日：2015-07-06

申请人： Ha-Na Kim ,  Dae-Hyun Jang ,  Jung-Ik Oh

发明人： Ha-Na Kim ,  Dae-Hyun Jang ,  Jung-Ik Oh

IPC分类号： H01L21/02 ,  H01L21/48 ,  H01L27/105 ,  H01L27/02

CPC分类号： H01L27/1052 ,  H01L21/481 ,  H01L21/4846 ,  H01L21/486 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A method of manufacturing a vertical memory device includes: providing a substrate including a cell array region and a peripheral circuit region; forming a mold structure in the cell array region; forming a mold protection film in a portion of the cell array region and the peripheral circuit region, the mold protection film contacting the mold structure; forming an opening for a common source line that passes through the mold structure and extends in a first direction perpendicular to a top surface of the substrate; forming a peripheral circuit contact hole that passes through the mold protection film and extends in the first direction in the peripheral circuit region; and simultaneously forming a first contact plug and a second contact plug, respectively, in the opening for the common source line and in the peripheral circuit contact hole.

摘要翻译： 制造垂直存储器件的方法包括：提供包括单元阵列区域和外围电路区域的衬底; 在电池阵列区域中形成模具结构; 在电池阵列区域和外围电路区域的一部分中形成保护膜，模具保护膜与模具结构接触; 形成用于通过所述模具结构并沿垂直于所述基板的顶表面的第一方向延伸的共同源极线的开口; 形成通过所述保护膜并在所述外围电路区域沿所述第一方向延伸的外围电路接触孔; 同时在公共源极线的开口和外围电路接触孔中分别形成第一接触插塞和第二接触插塞。

公开(公告)号：US20150311153A1

公开(公告)日：2015-10-29

申请号：US14795352

申请日：2015-07-09

申请人： Jung-Ik OH ,  Dae-Hyun JANG ,  Kyoung-Sub SHIN

发明人： Jung-Ik OH ,  Dae-Hyun JANG ,  Kyoung-Sub SHIN

IPC分类号： H01L23/528 ,  H01L27/115

CPC分类号： H01L27/11565 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, dummy area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.

摘要翻译： 根据示例性实施例，制造半导体器件的方法包括：通过在单元，第一焊盘区域，虚拟区域和第二焊盘上交替堆叠多个层间绝缘和牺牲层来形成包括上部和下部初级堆叠结构的预备叠层结构 基材面积; 去除所述第二焊盘区域上的所述上部初级堆叠结构的整个部分; 形成在所述第一和第二焊盘区域的部分上限定开口的第一掩模; 通过由第一掩模曝光的预备叠层结构的剩余部分来蚀刻对应于多个层间绝缘层和牺牲层中的一个的蚀刻深度; 并且重复地进行第一阶梯形成处理，其包括收缩第一掩模的侧面并通过由缩小的第一掩模暴露的多个层间绝缘和牺牲层的剩余部分蚀刻蚀刻深度。

公开(公告)号：US20140162420A1

公开(公告)日：2014-06-12

申请号：US14018578

申请日：2013-09-05

申请人： Jung-Ik OH ,  Dae-Hyun JANG ,  Kyoung-Sub SHIN

发明人： Jung-Ik OH ,  Dae-Hyun JANG ,  Kyoung-Sub SHIN

IPC分类号： H01L29/66

CPC分类号： H01L27/11565 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, sacrificial area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.

摘要翻译： 根据示例性实施例，制造半导体器件的方法包括：通过在电池，第一焊盘区域，牺牲区域和第二焊盘上交替堆叠多个层间绝缘和牺牲层来形成包括上部和下部预备堆叠结构的预备堆叠结构 基材面积; 去除所述第二焊盘区域上的所述上部初级堆叠结构的整个部分; 形成在所述第一和第二焊盘区域的部分上限定开口的第一掩模; 通过由第一掩模曝光的预备叠层结构的剩余部分来蚀刻对应于多个层间绝缘层和牺牲层中的一个的蚀刻深度; 并且重复地进行第一阶梯形成处理，其包括收缩第一掩模的侧面并通过由缩小的第一掩模暴露的多个层间绝缘和牺牲层的剩余部分蚀刻蚀刻深度。

公开(公告)号：US08557661B2

公开(公告)日：2013-10-15

申请号：US13314627

申请日：2011-12-08

申请人： Han-Geun Yu ,  Gyung-Jin Min ,  Seong-Soo Lee ,  Suk-Ho Joo ,  Yoo-Chul Kong ,  Dae-Hyun Jang

发明人： Han-Geun Yu ,  Gyung-Jin Min ,  Seong-Soo Lee ,  Suk-Ho Joo ,  Yoo-Chul Kong ,  Dae-Hyun Jang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11565 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11575 ,  H01L27/11582

摘要： A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.

摘要翻译： 一种制造半导体器件的方法包括在存储单元区域上形成存储单元，在连接区域上交替地形成牺牲层和绝缘中间层，以提供配置为电连接存储单元的布线，形成包括蚀刻掩模图案 在顶部牺牲层上的元件，在每个蚀刻掩模图案元件的每个侧壁上形成阻挡侧壁，形成第一光致抗蚀剂图案，选择性地将第一阻挡侧壁从存储器单元区域最远地覆盖并覆盖其它阻挡侧壁，蚀刻暴露顶部 牺牲层和绝缘中间层以暴露第二牺牲层，通过横向去除第一光致抗蚀剂图案至第二阻挡侧壁暴露的程度形成第二光致抗蚀剂图案，并将暴露的顶部和第二牺牲层和绝缘夹层蚀刻到 形成一个楼梯形状 d侧边缘部分。

公开(公告)号：US20120187471A1

公开(公告)日：2012-07-26

申请号：US13314627

申请日：2011-12-08

申请人： Han-Geun YU ,  Gyung-Jin MIN ,  Seong-Soo LEE ,  Suk-Ho JOO ,  Yoo-Chul KONG ,  Dae-Hyun JANG

发明人： Han-Geun YU ,  Gyung-Jin MIN ,  Seong-Soo LEE ,  Suk-Ho JOO ,  Yoo-Chul KONG ,  Dae-Hyun JANG

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/308

CPC分类号： H01L27/11565 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11575 ,  H01L27/11582

摘要： A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.

摘要翻译： 一种制造半导体器件的方法包括在存储单元区域上形成存储单元，在连接区域上交替地形成牺牲层和绝缘中间层，以提供配置为电连接存储单元的布线，形成包括蚀刻掩模图案 在顶部牺牲层上的元件，在每个蚀刻掩模图案元件的每个侧壁上形成阻挡侧壁，形成第一光致抗蚀剂图案，选择性地将第一阻挡侧壁从存储器单元区域最远地覆盖并覆盖其它阻挡侧壁，蚀刻暴露顶部 牺牲层和绝缘中间层以暴露第二牺牲层，通过横向去除第一光致抗蚀剂图案至第二阻挡侧壁暴露的程度形成第二光致抗蚀剂图案，并将暴露的顶部和第二牺牲层和绝缘夹层蚀刻到 形成一个楼梯形状 d侧边缘部分。