公开(公告)号：US20150311153A1

公开(公告)日：2015-10-29

申请号：US14795352

申请日：2015-07-09

Applicant: Jung-Ik OH ,  Dae-Hyun JANG ,  Kyoung-Sub SHIN

Inventor： Jung-Ik OH ,  Dae-Hyun JANG ,  Kyoung-Sub SHIN

IPC: H01L23/528 ,  H01L27/115

CPC classification number: H01L27/11565 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, dummy area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.

Abstract translation: 根据示例性实施例，制造半导体器件的方法包括：通过在单元，第一焊盘区域，虚拟区域和第二焊盘上交替堆叠多个层间绝缘和牺牲层来形成包括上部和下部初级堆叠结构的预备叠层结构 基材面积; 去除所述第二焊盘区域上的所述上部初级堆叠结构的整个部分; 形成在所述第一和第二焊盘区域的部分上限定开口的第一掩模; 通过由第一掩模曝光的预备叠层结构的剩余部分来蚀刻对应于多个层间绝缘层和牺牲层中的一个的蚀刻深度; 并且重复地进行第一阶梯形成处理，其包括收缩第一掩模的侧面并通过由缩小的第一掩模暴露的多个层间绝缘和牺牲层的剩余部分蚀刻蚀刻深度。

公开(公告)号：US20140162420A1

公开(公告)日：2014-06-12

申请号：US14018578

申请日：2013-09-05

Applicant: Jung-Ik OH ,  Dae-Hyun JANG ,  Kyoung-Sub SHIN

Inventor： Jung-Ik OH ,  Dae-Hyun JANG ,  Kyoung-Sub SHIN

IPC: H01L29/66

CPC classification number: H01L27/11565 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, sacrificial area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.

Abstract translation: 根据示例性实施例，制造半导体器件的方法包括：通过在电池，第一焊盘区域，牺牲区域和第二焊盘上交替堆叠多个层间绝缘和牺牲层来形成包括上部和下部预备堆叠结构的预备堆叠结构 基材面积; 去除所述第二焊盘区域上的所述上部初级堆叠结构的整个部分; 形成在所述第一和第二焊盘区域的部分上限定开口的第一掩模; 通过由第一掩模曝光的预备叠层结构的剩余部分来蚀刻对应于多个层间绝缘层和牺牲层中的一个的蚀刻深度; 并且重复地进行第一阶梯形成处理，其包括收缩第一掩模的侧面并通过由缩小的第一掩模暴露的多个层间绝缘和牺牲层的剩余部分蚀刻蚀刻深度。

公开(公告)号：US20130095654A1

公开(公告)日：2013-04-18

申请号：US13600025

申请日：2012-08-30

Applicant: Yong-Hyun KWON ,  Dae-Hyun JANG ,  Seong-Soo LEE ,  Kyoung-Sub SHIN

Inventor： Yong-Hyun KWON ,  Dae-Hyun JANG ,  Seong-Soo LEE ,  Kyoung-Sub SHIN

IPC: H01L21/768

CPC classification number: H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths.

Abstract translation: 根据本发明构思的示例性实施例，一种方法包括在基板上的单元图案之间形成单元图案和绝缘夹层。 在最上面的单元图案上形成包括初始接触孔和预接触孔的上绝缘层。 形成第一反射限制层图案和第一光致抗蚀剂层图案，用于暴露第一初步接触孔，同时覆盖初始和初步接触孔的入口部分。 在第一初步接触孔下方的层上进行第一蚀刻处理，以在比第一预接触孔的底部低的位置处露出电池图案。 重复第一反射限制层图案和第一光致抗蚀剂层图案的侧壁部分的部分去除处理以及通过预接触孔的底部的暴露层上的蚀刻工艺，以形成具有不同深度的接触孔。

公开(公告)号：US20140239376A1

公开(公告)日：2014-08-28

申请号：US14187548

申请日：2014-02-24

Applicant: Gang ZHANG ,  Kyoung-Sub SHIN

Inventor： Gang ZHANG ,  Kyoung-Sub SHIN

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/792 ,  H01L29/78

CPC classification number: H01L29/792 ,  H01L27/1052 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2481 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7926

Abstract: A memory device includes a plurality of channels, a plurality of first charge storage sites coupled to first sides of respective ones of the channels, and a plurality of second charge storage sites coupled to second sides of respective ones of the channels. The first charge storage sites correspond to first memory cells and the second charge storage sites coupled to second memory cells. At least one of the channels is a dummy channel not connected to a bit line, and a blocking layer is contiguously formed around the first and second charge storage sites and the channels.

Abstract translation: 存储器件包括多个通道，耦合到相应通道的第一侧的多个第一电荷存储位置以及耦合到相应通道的第二侧的多个第二电荷存储位置。 第一电荷存储位置对应于第一存储器单元和耦合到第二存储器单元的第二电荷存储位置。 通道中的至少一个是不连接到位线的虚拟通道，并且阻挡层围绕第一和第二电荷存储位置和通道连续地形成。

公开(公告)号：US20110143537A1

公开(公告)日：2011-06-16

申请号：US12913965

申请日：2010-10-28

Applicant: Jeong-Yun LEE ,  Ken TOKASHIKI ,  Kyoung-Sub SHIN ,  Jun-Ho YOON ,  Hong CHO

Inventor： Jeong-Yun LEE ,  Ken TOKASHIKI ,  Kyoung-Sub SHIN ,  Jun-Ho YOON ,  Hong CHO

IPC: H01L21/768

CPC classification number: H01J37/32165 ,  H01J37/32082 ,  H01J37/32155

Abstract: Provided are a method of fabricating a semiconductor device and synchronous pulse plasma etching equipment for the same. The method includes outputting a first radio frequency (RF) power and a control signal and outputting a second RF power. The first RF power is pulse-width modulated to have a first frequency and a first duty ratio, and is applied to a first electrode in a plasma etching chamber. The control signal includes information on a phase of the first RF power. The second RF power is pulse-width modulated to have the first frequency and a second duty ratio smaller than the first duty ratio, is applied to a corresponding second electrode among second electrodes in the plasma etching chamber, and is supplied for a time section in which the first RF power is supplied.

Abstract translation: 提供一种半导体器件和同步脉冲等离子体蚀刻设备的制造方法。 该方法包括输出第一射频（RF）功率和控制信号并输出​​第二RF功率。 第一RF功率被脉冲宽度调制以具有第一频率和第一占空比，并且被施加到等离子体蚀刻室中的第一电极。 控制信号包括关于第一RF功率的相位的信息。 第二RF功率被脉冲宽度调制成具有小于第一占空比的第一频率和第二占空比，被施加到等离子体蚀刻室中的第二电极中的对应的第二电极，并且被提供给 提供第一RF功率。

公开(公告)号：US20130134496A1

公开(公告)日：2013-05-30

申请号：US13599233

申请日：2012-08-30

Applicant: Sung-Soo AHN ,  O IK KWON ,  Bum-Soo KIM ,  Hyun-Sung KIM ,  Kyoung-Sub SHIN ,  Min-Kyung YUN ,  Seung-Pil CHUNG ,  Won-Bong JUNG

Inventor： Sung-Soo AHN ,  O IK KWON ,  Bum-Soo KIM ,  Hyun-Sung KIM ,  Kyoung-Sub SHIN ,  Min-Kyung YUN ,  Seung-Pil CHUNG ,  Won-Bong JUNG

IPC: H01L29/788 ,  H01L21/28

CPC classification number: H01L29/7883 ,  H01L21/7682 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42364 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.

Abstract translation: 一种制造半导体器件的方法，所述方法包括在衬底的上表面上形成隧道绝缘层，在隧道绝缘层的上表面上形成栅极图案，在栅极图案的侧壁上形成覆盖层图案，并且在 隧道绝缘层的上表面，蚀刻未被栅极图案或覆盖层图案覆盖的隧道绝缘层的一部分以形成隧道绝缘层图案，并且在衬底的上表面上形成第一绝缘层 以覆盖栅极图案，覆盖层图案和隧道绝缘层图案，其中第一绝缘层在封盖层图案之间具有气隙。

公开(公告)号：US20120126426A1

公开(公告)日：2012-05-24

申请号：US13351503

申请日：2012-01-17

Applicant: Kyoung-Sub SHIN

Inventor： Kyoung-Sub SHIN

IPC: H01L23/52

CPC classification number: H01L27/10888 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10885

Abstract: Provided may be a semiconductor memory device and a method of forming the semiconductor memory device. The memory device of example embodiments may include a bit line structure including a bit line on a semiconductor substrate, and a buried contact plug structure including a buried contact pad and a buried contact plug that extends in a lower portion of the bit line from one side of the bit line and connected to the buried contact pad. A width of the buried contact plug near a top surface of the buried contact pad may be greater than a width of the buried contact plug adjacent to the bit line.

Abstract translation: 可以提供半导体存储器件和形成半导体存储器件的方法。 示例性实施例的存储器件可以包括位线结构，其包括在半导体衬底上的位线，以及埋入式接触插塞结构，其包括埋入接触焊盘和埋入式接触插塞，所述埋入接触焊盘和埋入接触插塞从位于所述位线的一侧的一侧延伸 的位线并连接到埋地接触垫。 掩埋接触焊盘的顶表面附近的埋入接触插头的宽度可以大于与位线相邻的埋入接触插头的宽度。

公开(公告)号：US20120164809A1

公开(公告)日：2012-06-28

申请号：US13298732

申请日：2011-11-17

Applicant: Jun-Ho YOON ,  Kyoung-Sub SHIN ,  Jin-Wook LEE ,  Je-Woo HAN ,  Hyung-Yong KIM

Inventor： Jun-Ho YOON ,  Kyoung-Sub SHIN ,  Jin-Wook LEE ,  Je-Woo HAN ,  Hyung-Yong KIM

IPC: H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/32137 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, forming an amorphous silicon (a-Si) region adjacent to the gate pattern by implanting a dopant containing a Group IV or VIII element into portions of the semiconductor substrate, forming gate spacers on sidewalls of the gate pattern, forming a first cavity by etching the a-Si region and the substrate using a first etching process, forming a second cavity by etching the substrate, such that the second cavity expands a profile of the first cavity in lateral and vertical directions, and forming a strained semiconductor region in the second cavity.

Abstract translation: 制造半导体器件的方法包括在衬底上形成栅极图案，通过将含有IV或VIII族元素的掺杂剂注入到半导体衬底的部分中形成与栅极图案相邻的非晶硅（a-Si）区域，形成 在栅极图案的侧壁上的栅极间隔物，通过使用第一蚀刻工艺蚀刻a-Si区域和衬底形成第一腔体，通过蚀刻衬底形成第二腔体，使得第二腔体扩展第一腔体的轮廓 在横向和垂直方向上，并在第二腔中形成应变半导体区域。