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    Method of forming a step pattern structure
    2.
    发明授权
    Method of forming a step pattern structure 有权
    形成台阶图案结构的方法

    公开(公告)号：US09048193B2

    公开(公告)日：2015-06-02

    申请号：US13910734

    申请日：2013-06-05

    申请人： Jung-Ik Oh ,  Dae-Hyun Jang ,  Seong-Soo Lee ,  Han-Na Cho

    发明人： Jung-Ik Oh ,  Dae-Hyun Jang ,  Seong-Soo Lee ,  Han-Na Cho

    IPC分类号： H01L21/44 ,  H01L21/308 ,  H01L21/768 ,  H01L21/311 ,  H01L27/115 ,  H01L21/027

    CPC分类号： H01L21/308 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76838 ,  H01L21/76885 ,  H01L27/11575 ,  H01L27/11582

    摘要： A method of forming a multi-floor step pattern structure includes forming a stacked structure having alternating insulating interlayers and sacrificial layers on a substrate. A first photoresist pattern is formed on the stacked structure. A first preliminary step pattern structure is formed by etching portions of the stacked structure using the first photoresist pattern as an etching mask. A passivation layer pattern is formed on upper surfaces of the first photoresist pattern and the first preliminary step pattern structure. A second photoresist pattern is formed by removing a side wall portion of the first photoresist pattern exposed by the passivation layer pattern. A second preliminary step pattern structure is formed by etching exposed insulating interlayers and underlying sacrificial layers using the second photoresist pattern as an etching mask. The above steps may be repeated on the second preliminary step pattern structure to form the multi-floor step pattern structure.

    摘要翻译： 形成多层台阶图案结构的方法包括在基板上形成具有交替的绝缘夹层和牺牲层的堆叠结构。 第一光致抗蚀剂图案形成在堆叠结构上。 通过使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻层叠结构的部分来形成第一预备步骤图案结构。 钝化层图案形成在第一光致抗蚀剂图案和第一初步步骤图案结构的上表面上。 通过去除由钝化层图案暴露的第一光致抗蚀剂图案的侧壁部分形成第二光致抗蚀剂图案。 通过使用第二光致抗蚀剂图案作为蚀刻掩模蚀刻暴露的绝缘夹层和下面的牺牲层来形成第二初步步骤图案结构。 可以在第二预备步骤图案结构上重复上述步骤以形成多层台阶图案结构。

    Methods of manufacturing a vertical type semiconductor device
    3.
    发明授权
    Methods of manufacturing a vertical type semiconductor device 有权
    制造垂直型半导体器件的方法

    公开(公告)号：US08871591B2

    公开(公告)日：2014-10-28

    申请号：US13600025

    申请日：2012-08-30

    申请人： Yong-Hyun Kwon ,  Dae-Hyun Jang ,  Seong-Soo Lee ,  Kyoung-Sub Shin

    发明人： Yong-Hyun Kwon ,  Dae-Hyun Jang ,  Seong-Soo Lee ,  Kyoung-Sub Shin

    IPC分类号： H01L21/336

    CPC分类号： H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

    摘要： According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths.

    摘要翻译： 根据本发明构思的示例性实施例，一种方法包括在基板上的单元图案之间形成单元图案和绝缘夹层。 在最上面的单元图案上形成包括初始接触孔和预接触孔的上绝缘层。 形成第一反射限制层图案和第一光致抗蚀剂层图案，用于暴露第一初步接触孔，同时覆盖初始和初步接触孔的入口部分。 在第一初步接触孔下方的层上进行第一蚀刻处理，以在比第一预接触孔的底部低的位置处露出电池图案。 重复第一反射限制层图案和第一光致抗蚀剂层图案的侧壁部分的部分去除处理以及通过预接触孔的底部的暴露层上的蚀刻工艺，以形成具有不同深度的接触孔。

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130320486A1

    公开(公告)日：2013-12-05

    申请号：US13786853

    申请日：2013-03-06

    申请人： Jin-Hyuk YOO ,  Dae-hyun Jang ,  Yoo-Chul Kong ,  Kyoung-Sub Shin

    发明人： Jin-Hyuk YOO ,  Dae-hyun Jang ,  Yoo-Chul Kong ,  Kyoung-Sub Shin

    IPC分类号： H01L23/48

    CPC分类号： H01L27/1157 ,  H01L23/48 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

    摘要翻译： 提供一种半导体器件。 半导体器件包括设置在半导体衬底上的导电图案。 设置在导电图案上并且彼此位于相同水平面的第一和第二导电线。 隔离图案设置在第一和第二导线之间。 提供穿过第一导线和导电图案的第一垂直结构。 提供穿过第二导线和导电图案的第二垂直结构。 提供穿过导电图案并与隔离图案接触的辅助图案。

    FM TRANSMITTER, BROADCAST RECEIVER, AND METHOD FOR TRANSMITTING AUDIO
    5.
    发明申请
    FM TRANSMITTER, BROADCAST RECEIVER, AND METHOD FOR TRANSMITTING AUDIO 审中-公开
    FM发射机，广播接收机和发送音频的方法

    公开(公告)号：US20110287724A1

    公开(公告)日：2011-11-24

    申请号：US13090472

    申请日：2011-04-20

    申请人： Young-joong NOH ,  Dae-hyun JANG

    发明人： Young-joong NOH ,  Dae-hyun JANG

    IPC分类号： H04B1/04 ,  H04B1/40 ,  G06F3/048 ,  H04N5/44

    CPC分类号： H04H20/61 ,  H04B1/034

    摘要： A frequency modulation (FM) transmitter, a broadcast receiver having the same, and a method of transmitting an audio are provided. The FM transmitter selects a specific frequency from among frequencies in FM frequency band, which exclude a frequency in use, and transmits an audio signal over the selected specific frequency. Accordingly, the FM transmitter can transmit the audio signal using the confusion-free or interference-free frequency. As a result, a user can select a frequency to transmit the audio of the broadcast receiver easily.

    摘要翻译： 提供了一种频率调制（FM）发射机，具有该频率调制（FM）发射机，广播接收机以及发送音频的方法。 FM发射机从FM频带中的频率中选择一个特定的频率，排除使用频率，并在所选定的频率上发送音频信号。 因此，FM发射机可以使用无混乱或无干扰的频率来发送音频信号。 结果，用户可以选择频率来容易地发送广播接收机的音频。

    Mother glass for liquid crystal display and method of fabricating liquid crystal display using the same
    6.
    发明申请
    Mother glass for liquid crystal display and method of fabricating liquid crystal display using the same 有权
    用于液晶显示的母玻璃和使用其制造液晶显示器的方法

    公开(公告)号：US20080013034A1

    公开(公告)日：2008-01-17

    申请号：US11821146

    申请日：2007-06-22

    申请人： Jin Hwan Kim ,  Dae Hyun Jang

    发明人： Jin Hwan Kim ,  Dae Hyun Jang

    IPC分类号： G02F1/1333 ,  G02F1/13

    CPC分类号： G02F1/133351 ,  G02F2201/50

    摘要： A mother glass for a liquid crystal display and a method of fabricating a liquid crystal display using the same are disclosed. The mother glass includes a plurality of cell areas where a plurality of thin films is formed on a substrate, a dummy area disposed outside the plurality of cell areas on the substrate, and a passivation layer. The passivation layer is coated on substantially an overall portion of the plurality of cell areas, and formed in a straight line-like band form along a transverse direction in the dummy area to isolate the cell areas from each other in a longitudinal direction.

    摘要翻译： 公开了一种用于液晶显示器的母玻璃以及使用其制造液晶显示器的方法。 母玻璃包括在基板上形成多个薄膜的多个单元区域，设置在基板上的多个单元区域的外侧的虚设区域和钝化层。 钝化层涂覆在多个单元区域的基本上整个部分上，并且在虚拟区域中沿着横向形成为直线状带状，以在纵向方向上隔离单元格区域。

    Method of forming a metal wiring in a semiconductor device
    7.
    发明申请
    Method of forming a metal wiring in a semiconductor device 有权
    在半导体器件中形成金属布线的方法

    公开(公告)号：US20070006451A1

    公开(公告)日：2007-01-11

    申请号：US11475166

    申请日：2006-06-27

    申请人： Yong-Woo Lee ,  Jae-Seung Hwang ,  Dae-Hyun Jang

    发明人： Yong-Woo Lee ,  Jae-Seung Hwang ,  Dae-Hyun Jang

    IPC分类号： H01R43/00

    CPC分类号： H01L21/7685 ,  H01L21/32139 ,  Y10T29/49117

    摘要： Example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device. Other example embodiments of the present invention relate to a method of forming a metal wiring in a semiconductor device without a generation of a bridge between adjacent metal wirings. In a method of forming a metal wiring in a semiconductor device, at least one metal layer and at least one barrier layer may be sequentially formed on a substrate. A metal blocking layer may be formed on the at least one barrier metal layer. A hard mask layer may be formed on the metal blocking layer. A hard mask pattern may be formed on the metal blocking layer by etching the hard mask layer without an exposure of the at least one barrier metal layer. A metal blocking layer pattern may be formed on the at least one barrier metal layer by etching the metal blocking layer using the hard mask pattern as an etching mask. The metal wiring having at least one metal layer pattern and at least one barrier metal layer pattern may be formed on the substrate by etching the at least one barrier metal layer and the at least one metal layer using the hard mask pattern as an etching mask. The metal wiring having a reduced width may be obtained without a failure (e.g., a bridge).

    摘要翻译： 本发明的示例性实施例涉及在半导体器件中形成金属布线的方法。 本发明的其他示例性实施例涉及在半导体器件中形成金属布线而不在相邻金属布线之间产生桥的方法。 在半导体器件中形成金属布线的方法中，可以在衬底上依次形成至少一个金属层和至少一个阻挡层。 金属阻挡层可以形成在至少一个阻挡金属层上。 可以在金属阻挡层上形成硬掩模层。 可以通过在不暴露至少一个阻挡金属层的情况下蚀刻硬掩模层而在金属阻挡层上形成硬掩模图案。 通过使用硬掩模图案作为蚀刻掩模蚀刻金属阻挡层，可以在至少一个阻挡金属层上形成金属阻挡层图案。 通过使用硬掩模图案作为蚀刻掩模蚀刻至少一个阻挡金属层和至少一个金属层，可以在基板上形成具有至少一个金属层图案和至少一个阻挡金属层图案的金属布线。 可以获得具有减小的宽度的金属布线而没有故障（例如桥）。

    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    9.
    发明申请
    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    垂直存储器件及其制造方法

    公开(公告)号：US20160133630A1

    公开(公告)日：2016-05-12

    申请号：US14792114

    申请日：2015-07-06

    申请人： Ha-Na KIM ,  Dae-Hyun JANG ,  Jung-Ik OH

    发明人： Ha-Na KIM ,  Dae-Hyun JANG ,  Jung-Ik OH

    IPC分类号： H01L27/105 ,  H01L21/48 ,  H01L27/02

    CPC分类号： H01L27/1052 ,  H01L21/481 ,  H01L21/4846 ,  H01L21/486 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    摘要： A method of manufacturing a vertical memory device includes: providing a substrate including a cell array region and a peripheral circuit region; forming a mold structure in the cell array region; forming a mold protection film in a portion of the cell array region and the peripheral circuit region, the mold protection film contacting the mold structure; forming an opening for a common source line that passes through the mold structure and extends in a first direction perpendicular to a top surface of the substrate; forming a peripheral circuit contact hole that passes through the mold protection film and extends in the first direction in the peripheral circuit region; and simultaneously forming a first contact plug and a second contact plug, respectively, in the opening for the common source line and in the peripheral circuit contact hole.

    摘要翻译： 制造垂直存储器件的方法包括：提供包括单元阵列区域和外围电路区域的衬底; 在电池阵列区域中形成模具结构; 在电池阵列区域和外围电路区域的一部分中形成保护膜，模具保护膜与模具结构接触; 形成用于通过所述模具结构并沿垂直于所述基板的顶表面的第一方向延伸的共同源极线的开口; 形成通过所述保护膜并沿所述外围电路区域沿所述第一方向延伸的外围电路接触孔; 同时在公共源极线的开口和外围电路接触孔中分别形成第一接触插塞和第二接触插塞。