公开(公告)号：US20140281043A1

公开(公告)日：2014-09-18

申请号：US13841916

申请日：2013-03-15

Applicant: Tommi M. Jokinen ,  David B. Kramer ,  Kun Xu

Inventor： Tommi M. Jokinen ,  David B. Kramer ,  Kun Xu

IPC: G06F13/12

CPC classification number: G06F13/126

Abstract: A data processing device includes a plurality of devices, a processor core, a memory, and a queue manager. The processor core stores one or more commands in a command queue of the memory to be executed by the plurality of devices to implement a data transfer path. The queue manager stores a frame queue for each of the plurality of devices. Each frame queue includes a first field having a pointer to an address of the command queue, and a second field to identify a next-in-sequence frame queue. A first device stores a data descriptor in the frame queue of the second device to initiate a data transfer from the first device to the second device. The data descriptor includes a field to indicate an offset value from the address of the command queue to a location of a command to be executed by the second device.

Abstract translation: 数据处理设备包括多个设备，处理器核心，存储器和队列管理器。 处理器核心将一个或多个命令存储在由多个设备执行的存储器的命令队列中以实现数据传输路径。 队列管理器存储多个设备中的每一个的帧队列。 每个帧队列包括具有指向命令队列的地址的指针的第一字段和用于标识下一个序列帧队列的第二字段。 第一设备将数据描述符存储在第二设备的帧队列中，以启动从第一设备到第二设备的数据传输。 数据描述符包括用于指示从命令队列的地址到由第二设备执行的命令的位置的偏移值的字段。

公开(公告)号：US08615614B2

公开(公告)日：2013-12-24

申请号：US13307271

申请日：2011-11-30

Applicant: Kun Xu ,  Tommi M. Jokinen ,  David B. Kramer

Inventor： Kun Xu ,  Tommi M. Jokinen ,  David B. Kramer

IPC: G06F13/28 ,  G06F12/00

CPC classification number: G06F13/28

Abstract: A method includes generating, by a first software process of the data processing system, a source partition descriptor for a DMA job which requires access to a first partition of a memory which is assigned to a second software process of the data processing system and not assigned to the first software process. The source partition descriptor comprises a partition identifier which identifies the first partition of the memory. The DMA unit receives the source partition descriptor and generates a destination partition descriptor for the DMA job. Generating the destination partition descriptor includes translating, by the DMA unit, the partition identifier to a buffer pool identifier which identifies a physical address within the first partition of the memory which is assigned to the second software process; and storing, by the DMA unit, the buffer pool identifier in the destination partition descriptor.

Abstract translation: 一种方法包括通过数据处理系统的第一软件过程生成用于DMA作业的源分区描述符，其需要访问分配给数据处理系统的第二软件处理并且未分配的存储器的第一分区 到第一个软件过程。 源分区描述符包括标识存储器的第一分区的分区标识符。 DMA单元接收源分区描述符，并为DMA作业生成目标分区描述符。 生成目的地分区描述符包括由DMA单元将分区标识符转换为标识分配给第二软件进程的存储器的第一分区内的物理地址的缓冲池标识符; 并且由DMA单元将缓冲池标识符存储在目的地分区描述符中。

公开(公告)号：US08447897B2

公开(公告)日：2013-05-21

申请号：US13168331

申请日：2011-06-24

Applicant: Kun Xu ,  Tommi M. Jokinen ,  David B. Kramer

Inventor： Kun Xu ,  Tommi M. Jokinen ,  David B. Kramer

IPC: G06F3/00 ,  G06F5/00

CPC classification number: G06F13/28

Abstract: A method for controlling bandwidth in a direct memory access (DMA) unit of a computer processing system, the method comprising: assigning a DMA job to a selected DMA engine; starting a source timer; and issuing a request to read a next section of data for the DMA job. If a sufficient amount of the data was not obtained, allowing the DMA engine to wait until the source timer reaches a specified value before continuing to read additional data for the DMA job.

Abstract translation: 一种用于控制计算机处理系统的直接存储器访问（DMA）单元中的带宽的方法，所述方法包括：将DMA作业分配给所选择的DMA引擎; 启动源计时器; 并发出读取DMA作业的下一个数据部分的请求。 如果未获得足够数量的数据，则允许DMA引擎等待，直到源定时器达到指定值，然后再继续读取DMA作业的其他数据。

公开(公告)号：US20110238934A1

公开(公告)日：2011-09-29

申请号：US12748600

申请日：2010-03-29

Applicant: Kun Xu ,  David B Kramer ,  James A. Welker

Inventor： Kun Xu ,  David B Kramer ,  James A. Welker

IPC: G06F12/00

CPC classification number: G06F13/1689 ,  G06F12/0215

Abstract: A data processing system employs a scheduler to schedule pending memory access requests and a memory controller to service scheduled pending memory access requests. The memory access requests are asynchronously scheduled with respect to the clocking of the memory. The scheduler is operated using a clock signal with a frequency different from the frequency of the clock signal used to operate the memory controller. The clock signal used to clock the scheduler can have a lower frequency than the clock used by a memory controller. As a result, the scheduler is able to consider a greater number of pending memory access requests when selecting the next pending memory access request to be submitted to the memory for servicing and thus the resulting sequence of selected memory access requests is more likely to be optimized for memory access throughput.

Abstract translation: 数据处理系统使用调度器来调度待执行的存储器访问请求和存储器控制器来服务预定的未决存储器访问请求。 存储器访问请求相对于存储器的时钟被异步调度。 使用频率不同于用于操作存储器控制器的时钟信号的频率的时钟信号来操作调度器。 用于时钟调度器的时钟信号的频率可能低于存储器控制器使用的时钟频率。 因此，当选择要提交给存储器进行服务的下一个未决的存储器访问请求时，调度器能够考虑更多数量的待处理存储器访问请求，因此所选择的存储器访问请求的结果序列更有可能被优化 用于内存访问吞吐量。

公开(公告)号：US07912069B2

公开(公告)日：2011-03-22

申请号：US11299645

申请日：2005-12-12

Applicant: David B. Kramer ,  David P. Sonnier

Inventor： David B. Kramer ,  David P. Sonnier

IPC: H04L12/28 ,  H04J3/16 ,  H04J3/24

CPC classification number: H04L12/5601 ,  H04L49/90 ,  H04L49/9073 ,  H04L2012/5652 ,  H04L2012/5658 ,  H04L2012/5667 ,  H04L2012/5681

Abstract: A virtual segmentation system and a method of operating the same. In one embodiment, the virtual segmentation system includes a protocol data unit receiver subsystem configured to (i) receive at least a portion of a protocol data unit and (ii) store the at least a portion of the protocol data unit in at least one block, and a virtual segmentation subsystem, associated with the protocol data unit receiver subsystem, configured to perform virtual segmentation on the protocol data unit by segmenting the at least one block when retrieved without reassembling an entirety of the protocol data unit.

Abstract translation: 虚拟分割系统及其操作方法。 在一个实施例中，虚拟分段系统包括协议数据单元接收器子系统，其被配置为（i）接收协议数据单元的至少一部分，以及（ii）将协议数据单元的至少一部分存储在至少一个块中 以及与所述协议数据单元接收器子系统相关联的虚拟分段子系统，被配置为通过在未重新组合所述协议数据单元的整体的情况下分段所述至少一个块来对所述协议数据单元执行虚拟分段。

公开(公告)号：US07850013B1

公开(公告)日：2010-12-14

申请号：US11821007

申请日：2007-06-21

Applicant: David B. Kramer ,  Peter Williams

Inventor： David B. Kramer ,  Peter Williams

IPC: E05B73/00

CPC classification number: E05C19/003 ,  E05B67/36 ,  E05B73/0082 ,  H05K7/1489 ,  H05K7/186 ,  Y10S70/64 ,  Y10T70/5097 ,  Y10T70/5168

Abstract: A locking mechanism to minimize access to a portion of a rack-mounted electronic device is provided. The locking mechanism includes a bar supported at one end to a first vertical post of the rack, and a locking member supported at a second end of the bar for locking to a second vertical post. In one embodiment, the bar is pivotally supported at the one end to the first post. The bar is movable between an open position where unimpeded access to a first portion of the electronic device is provided, and a closed position to restrict removal of components from the first portion of the electronic device. A clearance space may provided between the bar and the electronic device in the closed position to allow a user to access an electronic component to remove power from the component, but not to fully remove the component without unlocking the locking member.

Abstract translation: 提供了一种用于最小化对机架安装的电子设备的一部分的访问的锁定机构。 所述锁定机构包括在一端支撑到所述齿条的第一垂直柱的杆，以及支撑在所述杆的第二端处以锁定到第二垂直柱的锁定构件。 在一个实施例中，杆在一端枢转地支撑到第一柱。 该杆可以在设置有电子设备的第一部分的无阻碍的通路的打开位置和用于限制从电子设备的第一部分移除部件的关闭位置之间移动。 在关闭位置的杆和电子设备之间可以设置间隙空间，以允许使用者访问电子部件以从组件移除动力，但是不能在不解锁锁定构件的情况下完全移除部件。

公开(公告)号：US07411972B2

公开(公告)日：2008-08-12

申请号：US10768764

申请日：2004-01-30

Applicant: Asif Q. Khan ,  David B. Kramer

Inventor： Asif Q. Khan ,  David B. Kramer

IPC: H04L12/403 ,  H04L12/56 ,  H04J14/00

CPC classification number: H04L41/00

Abstract: In a communication system comprising a link layer device connectable to one or more physical layer devices, at least a given one of a plurality of ports of the one or more physical layer devices is designated as a port for which status information is to be requested by the link layer device on a more frequent basis than such information is to be requested for one or more other ports of the plurality of ports. The ports are then polled by the link layer device in accordance with a non-linear polling sequence such that the at least one designated port is polled more frequently than the one or more other ports. The designated port may comprise a port to which the link layer device transmits data in conjunction with a current data transfer. The non-linear polling sequence may thus be altered dynamically based on particular data transfers that are occurring between a link layer device and a physical layer device in a communication system.

Abstract translation: 在包括可连接到一个或多个物理层设备的链路层设备的通信系统中，一个或多个物理层设备的多个端口中的至少一个给定的一个被指定为要由其请求状态信息的端口 对于多个端口中的一个或多个其他端口，要求比这种信息更频繁的链路层设备。 然后根据非线性轮询序列由链路层设备轮询端口，使得至少一个指定端口比一个或多个其他端口更频繁地轮询。 指定端口可以包括链路层设备结合当前数据传输发送数据的端口。 因此，可以基于在通信系统中的链路层设备和物理层设备之间发生的特定数据传输来动态地改变非线性轮询序列。

公开(公告)号：US20070283144A1

公开(公告)日：2007-12-06

申请号：US11422063

申请日：2006-06-02

Applicant: David B. Kramer ,  Chris P. Thron ,  Bernard Karl Gunther

Inventor： David B. Kramer ,  Chris P. Thron ,  Bernard Karl Gunther

IPC: H04L9/00

CPC classification number: H04L63/0263 ,  H04L63/101

Abstract: A method, data processing system, and computer program product are provided for retrieving access rules using a plurality of subtables. An incoming packet that includes fields of data is received from a network. A key is formed from the fields, the key includes a number of subkeys. The subkeys are selected and each of the selected subkeys is used to search a different subtable. If a subtable entry is a pointer, a next level subtable is searched until a failure or data is encountered. If a failure occurs, a default rule is applied. If data is encountered, the key is masked using a stored mask value. The resulting masked key is compared to a stored rule. If they match, the identified rule is applied, otherwise the default rule is applied.

Abstract translation: 提供了一种方法，数据处理系统和计算机程序产品，用于使用多个子表检索访问规则。 从网络接收包括数据字段的传入分组。 密钥由字段形成，密钥包括多个子密钥。 选择子项，并且使用每个所选择的子项来搜索不同的子表。 如果子表项是指针，则搜索下一级子表，直到出现故障或数据遇到。 如果发生故障，则应用默认规则。 如果遇到数据，密钥将使用存储的掩码值进行掩码。 将结果掩码的密钥与存储的规则进行比较。 如果匹配，则应用已识别的规则，否则应用默认规则。

公开(公告)号：US07159061B2

公开(公告)日：2007-01-02

申请号：US10744567

申请日：2003-12-23

Applicant: Asif Q. Khan ,  David B. Kramer

Inventor： Asif Q. Khan ,  David B. Kramer

IPC: H03M7/20 ,  G06F12/00 ,  G06F13/14 ,  G06F13/00 ,  G06F11/00

CPC classification number: G06F13/385

Abstract: Techniques are disclosed for flexible allocation of address pins of an interface bus to particular sub-buses of the interface bus. The interface bus is between at least one physical layer device and a link layer device in a communication system. Each of the sub-buses has an interface block of the link layer device associated therewith, the interface bus being configurable to carry a composite address signal having a plurality of portions each associated with one of the address pins of the interface bus. The interface blocks of the link layer device are controlled such that each of at least a subset of the interface blocks utilizes only particular ones of the address pins that are controllably allocated to the associated sub-bus in accordance with configuration information stored in the link layer device. The composite address signal is generated as a combination of address outputs of the interface blocks.

Abstract translation: 公开了用于将接口总线的地址引脚灵活分配给接口总线的特定子总线的技术。 接口总线在通信系统中的至少一个物理层设备和链路层设备之间。 每个子总线具有与其相关联的链路层设备的接口块，该接口总线可配置为承载具有多个部分的复合地址信号，每个部分与接口总线的一个地址引脚相关联。 控制链路层设备的接口块，使得接口块的至少一个子集中的每一个仅使用根据存储在链路层中的配置信息可控地分配给相关联的子总线的特定地址引脚 设备。 复合地址信号作为接口块的地址输出的组合生成。

公开(公告)号：US09436626B2

公开(公告)日：2016-09-06

申请号：US13570874

申请日：2012-08-09

Applicant: Bryan D. Marietta ,  Gary L. Whisenhunt ,  Kumar K. Gala ,  David B. Kramer

Inventor： Bryan D. Marietta ,  Gary L. Whisenhunt ,  Kumar K. Gala ,  David B. Kramer

IPC: G06F13/26 ,  G06F9/50 ,  G06F9/45 ,  G06F13/14 ,  G06F13/24 ,  G06F9/455

CPC classification number: G06F13/26 ,  G06F9/45533 ,  G06F9/5077 ,  G06F13/14 ,  G06F13/24

Abstract: A method and circuit for a data processing system (200) provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers (35-38) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.

Abstract translation: 用于数据处理系统（200）的方法和电路通过将所接收的中断请求相关联的中断标识符，分区标识符，线程标识符和优先权级别存储在位于专用寄存器（35-38）中来提供基于处理器的分区优先级阻塞机制 在处理器核心（26）上，以便在分区的基础上实现快速有效的中断优先级阻塞。