-
公开(公告)号：US07562275B2
公开(公告)日：2009-07-14
申请号：US11531832
申请日：2006-09-14
CPC分类号： G01R31/31713 , G01R1/0408 , G01R31/31701 , G01R31/318544
摘要： A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and converter circuit that provides a logic level indicative of a test mode of the integrated circuit in response to a corresponding input level. The technique substantially reduces or eliminates false detections of the test mode and substantially reduces or eliminates falsely enabling other (e.g., functional) mode(s) of the integrated circuit.
摘要翻译： 用于增加集成电路的终端的功能而不增加集成电路的终端数量的技术利用至少一个三电平终端和转换器电路，其提供指示集成电路的测试模式的逻辑电平，以响应于 相应的输入电平。 该技术基本上减少或消除了测试模式的错误检测，并且基本上减少或消除了错误地启用集成电路的其他（例如，功能）模式。
-
公开(公告)号：US07187216B2
公开(公告)日：2007-03-06
申请号：US10878198
申请日：2004-06-28
IPC分类号： H03K21/00
CPC分类号： H03K23/66 , H03L7/193 , H03L7/1976
摘要： A phase selectable divider circuit includes a select circuit receiving a plurality of signals having a common frequency and a different phase. One of the plurality of signals, having a first phase, is selected as a selector circuit output signal. A first value corresponding to the first phase is summed with a second value corresponding to a phase offset from the first phase to generate a sum indicative thereof. That sum is used to select a second one of the signals having a second phase as the next selector circuit output signal. As successive sums are generated, a pulse train is supplied by selector circuit having a desired frequency.
摘要翻译： 相位选择分频电路包括接收具有共同频率和不同相位的多个信号的选择电路。 选择具有第一相位的多个信号中的一个作为选择器电路输出信号。 对应于第一相位的第一值与对应于从第一相位的相位偏移的第二值相加，以产生指示其的和。 该和用于选择具有第二相位的第二信号作为下一个选择器电路输出信号。 当产生连续的和时，由选择器电路提供具有期望频率的脉冲串。
-
公开(公告)号：US07113009B2
公开(公告)日：2006-09-26
申请号：US10807852
申请日：2004-03-24
IPC分类号： H03K25/00
CPC分类号： H03K21/40 , H03K21/08 , H03K23/667
摘要： A divider is disclosed herein. The divider includes a sequence of divide stages programmably coupled to provide a variety of divide ratios. The divider also includes one or more multiplexers to feedback the output of a divide stage to the input of a divide stage earlier in the sequence of divide stages. The divider may also include duty cycle correction circuitry and self correction logic to correct abnormal logic states. The divide stages can operate in synchronism with each other. Multiplexer functionality, self correction circuitry functionality, and divide stage functionality may be implemented in a combination latch circuit.
摘要翻译： 本文公开了一种分频器。 分频器包括可编程地耦合以提供各种分频比的分频级序列。 分频器还包括一个或多个多路复用器，用于将分频级的输出反馈到除法级序列之前的分频级的输入端。 分频器还可以包括占空比校正电路和用于校正异常逻辑状态的自校正逻辑。 分级阶段可以相互同步运行。 多路复用器功能，自校正电路功能和分频功能可以在组合锁存电路中实现。
-
14.发明授权Energy-to-pulse converter systems, devices, and methods wherein the output frequency is greater than the calculation frequency and having output phasing 有权能量到脉冲转换器系统，装置和方法，其中输出频率大于计算频率并具有输出相位公开(公告)号：US06522982B1
公开(公告)日：2003-02-18
申请号：US09405370
申请日：1999-09-24
IPC分类号： G01B1302
CPC分类号： G06J1/00
摘要： An energy-to-pulse (E2P) converter for converting analog voltage and current measurements into digital power consumption readout that has an improved output frequency range and can eliminate the potential information loss in a multiple-wires and multiple-phases power distribution system without added complex hardware. The E2P uses a threshold value T in determining the output pulse count which represents the energy/power consumption. The energy consumption E is updated every cycle of a first clock rate F1 during which a power P calculation is performed following a voltage V and a current I analog-to digital conversion. The updated energy consumption E is then divided by the threshold value T to determine the number of pulses that correspond to the power consumption. The number of pulses are output at a second clock rate F2. In so doing, more than one pulse can be generated for each P calculation thereby improving the output frequency range. To prevent complete signal overlaps that may lead to information loss in multiple-wires and multiple-phases power system, the pulse output for each wire can be programmed to have a different phase such that the pulses from the pulse outputs, which are all synchronous with each other, are non-overlapped.
摘要翻译： 一种用于将模拟电压和电流测量转换为数字功耗读数的能量脉冲（E2P）转换器，具有改进的输出频率范围，可以消除多线和多相配电系统中的潜在信息丢失，无需添加 复杂的硬件。 E2P在确定表示能量/功耗的输出脉冲计数时使用阈值T. 在第一时钟速率F1的每个周期更新能量消耗E，在第一时钟速率F1期间，在电压V和电流I模数转换之后执行功率P计算。 然后将更新的能量消耗E除以阈值T以确定与功耗相对应的脉冲数。 以第二时钟速率F2输出脉冲数。 这样做，可以为每个P计算产生多于一个脉冲，从而改善输出频率范围。 为了防止可能导致多线和多相电力系统中的信息丢失的完整的信号重叠，每条线路的脉冲输出可以被编程为具有不同的相位，使得来自脉冲输出的脉冲全部与 彼此不重叠。
-
15.发明授权Single phase bi-directional electrical measurement systems and methods using ADCs 有权单相双向电气测量系统和使用ADC的方法公开(公告)号：US06417792B1
公开(公告)日：2002-07-09
申请号：US09484688
申请日：2000-01-18
申请人： Eric T. King , Douglas F. Pastorello , Bruce P. Del Signore , Victor Aguilar , Frank Den Breejen , William F. Gardei
发明人： Eric T. King , Douglas F. Pastorello , Bruce P. Del Signore , Victor Aguilar , Frank Den Breejen , William F. Gardei
IPC分类号： H03M300
CPC分类号： G01R21/133
摘要： An analog to digital converter system includes first and second delta sigma converters, a calculation engine, and a serial interface on a single chip. The calculation engine is configured to calculate energy, power, rms current and voltage for single phase 2 or 3 wire power meters. Voltage and current are measured with a shunt or transformer, and a divider or transformer, respectively. The serial interface is bidirectional for communication with a microprocessor or controller, and provides a fixed width programmable frequency output proportional to energy. The digital converter system is user system calibratible.
摘要翻译： 模数转换器系统包括单个芯片上的第一和第二Δ-Σ转换器，计算引擎和串行接口。 计算引擎配置为计算单相2线或3线功率计的能量，功率，均方根电流和电压。 电压和电流分别用分流器或变压器以及分压器或变压器来测量。 串行接口是双向的，与微处理器或控制器通信，并提供与能量成比例的固定宽度的可编程频率输出。 数字转换器系统是用户系统校准的。
-
公开(公告)号：US06369634B1
公开(公告)日：2002-04-09
申请号：US09484128
申请日：2000-01-15
IPC分类号： H03H1126
CPC分类号： H03H17/0286 , H03H17/0036
摘要： A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system filter includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value. The method filter includes further delaying production of the selected signal with a second comparison utilizing a second predetermined value of a further reduced frequency clock.
摘要翻译： 延迟系统包括被配置为接收所选择的输入信号的第一滤波器和用于激活第一滤波器以产生作为所选输入信号的函数的延迟输出信号的第一机构。 延迟系统滤波器包括第二滤波器，其被配置为从所述第一滤波器接收信号以对由所述第一滤波器接收的信号施加附加延迟;以及第二机制，用于激活第二滤波器以产生延迟信号，该延迟信号是 从第一滤波器接收的信号。 延迟系统还包括用于跟踪来自时钟参考的时间的分频器系统。 延迟系统通过采用预定的时钟信号采样所选择的信号来实现延迟接收信号的方法，并且将延迟到缩小频率时钟与预定值的比较程度的时间产生所选择的信号。 该方法滤波器包括利用进一步降低的频率时钟的第二预定值的第二比较进一步延迟所选信号的产生。
-
公开(公告)号：US08020010B2
公开(公告)日：2011-09-13
申请号：US12144803
申请日：2008-06-24
CPC分类号： G06F1/3203 , G06F1/12 , G06F1/3225 , G06F1/3275 , G11C5/14 , G11C17/146 , G11C17/18 , Y02D10/14
摘要： A memory power controller comprises a clock generation circuitry for generating a first clock signal and a second clock signal responsive to a source clock and a determination that the source clock has a period greater than a predetermined value. The first clock is generated responsive to a determination that the source clock has a period greater than the predetermined value and the second clock is generated responsive to the determination that the source clock has a period less than the predetermined value. Memory time-out circuitry generates a memory enable/disable signal to control operation of an associated memory responsive to the clock signal and the determination that the source clock has a period greater than the predetermined value. The memory time-out circuitry further synchronizes the memory enable/disable signal with the source clock.
摘要翻译： 存储器功率控制器包括用于响应于源时钟产生第一时钟信号和第二时钟信号的时钟产生电路以及源时钟具有大于预定值的周期的确定。 响应于源时钟具有大于预定值的周期的确定产生第一时钟，并且响应于源时钟具有小于预定值的周期的确定而产生第二时钟。 存储器超时电路产生存储器使能/禁止信号，以响应于时钟信号来控制相关存储器的操作，以及确定源时钟具有大于预定值的周期。 存储器超时电路进一步使存储器使能/禁止信号与源时钟同步。
-
公开(公告)号：US08010819B2
公开(公告)日：2011-08-30
申请号：US12255127
申请日：2008-10-21
申请人： Douglas F. Pastorello , Douglas Holberg , William Gene Durbin , Biranchinath Sahu , Golam R. Chowdhury
发明人： Douglas F. Pastorello , Douglas Holberg , William Gene Durbin , Biranchinath Sahu , Golam R. Chowdhury
CPC分类号： G06F1/3203 , H03K19/0016
摘要： A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.
摘要翻译： 微控制器单元包括用于产生第一控制信号以开始微控制器单元的昏迷模式的处理器。 响应于第一控制信号的控制逻辑在第一电平产生使能信号，并且控制逻辑还响应于第二控制信号，以在第二电平产生使能信号。 电压调节器从输入电压产生调节电压。 电压调节器关闭，以响应于在第一电平的使能信号提供零伏调节电压，并且上电以响应于在第二电平的使能信号提供处于工作电平的调节电压。
-
公开(公告)号：US06531906B2
公开(公告)日：2003-03-11
申请号：US10007588
申请日：2001-12-05
IPC分类号： H03H1126
CPC分类号： H03H17/0286 , H03H17/0036
摘要： A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system further includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value. The method further includes further delaying production of the selected signal with a second comparison utilizing a second predetermined value of a further reduced frequency clock.
摘要翻译： 延迟系统包括被配置为接收所选择的输入信号的第一滤波器和用于激活第一滤波器以产生作为所选输入信号的函数的延迟输出信号的第一机构。 所述延迟系统还包括第二滤波器，其被配置为从所述第一滤波器接收信号以对由所述第一滤波器接收的信号施加附加延迟;以及第二机构，用于激活所述第二滤波器以产生延迟信号，所述延迟信号是 从第一滤波器接收的信号。 延迟系统还包括用于跟踪来自时钟参考的时间的分频器系统。 延迟系统通过采用预定的时钟信号采样所选择的信号来实现延迟接收信号的方法，并且将延迟到缩小频率时钟与预定值的比较程度的时间产生所选择的信号。 该方法还包括进一步延迟所选择的信号的产生，并利用进一步降低的频率时钟的第二预定值进行第二比较。
-
公开(公告)号：US5923273A
公开(公告)日：1999-07-13
申请号：US751708
申请日：1996-11-18
CPC分类号： H03H17/06 , H03H17/0226
摘要： A reduced power FIR filter may be utilized as the digital decimation filter for a delta sigma ADC. The FIR filter utilizes a serial bit stream which is part of the control path of the filter. Thus, operations of the circuitry which comprises the filter may be controlled depending upon the data presented at the output of the delta sigma modulator. In particular, filter operations may be enabled only for a given digital state, for example, a digital 1 state. Thus, the filter operations may be enabled only for typically half of the bits from the serial bit stream and the power usage of the digital filter is significantly reduced.
摘要翻译： 降低功率FIR滤波器可以用作Δ西格玛ADC的数字抽取滤波器。 FIR滤波器利用串行比特流，该比特流是滤波器的控制路径的一部分。 因此，可以根据呈现在Δ-Σ调制器的输出处的数据来控制包括滤波器的电路的操作。 特别地，可以仅针对给定的数字状态（例如，数字1状态）使能滤波器操作。 因此，滤波器操作可以仅来自串行比特流的典型的一半比特，并且数字滤波器的功率使用量显着降低。
-
-
-
-
-
-
-
-
-
搜索结果
29 条记录 (耗时 0.017 秒)
