公开(公告)号：US07441131B2

公开(公告)日：2008-10-21

申请号：US11240923

申请日：2005-09-30

申请人： Douglas F. Pastorello ,  Douglas Holberg ,  William Gene Durbin ,  Biranchinath Sahu ,  Golam R. Chowdhury

发明人： Douglas F. Pastorello ,  Douglas Holberg ,  William Gene Durbin ,  Biranchinath Sahu ,  Golam R. Chowdhury

IPC分类号： G06F1/00 ,  G05F1/00

CPC分类号： G06F1/3203 ,  H03K19/0016

摘要： A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.

摘要翻译： 微控制器单元包括用于产生第一控制信号以开始微控制器单元的昏迷模式的处理器。 响应于第一控制信号的控制逻辑在第一电平产生使能信号，并且控制逻辑还响应于第二控制信号，以在第二电平产生使能信号。 电压调节器从输入电压产生调节电压。 电压调节器关闭，以响应于在第一电平的使能信号提供零伏调节电压，并且上电以响应于在第二电平的使能信号提供处于工作电平的调节电压。

公开(公告)号：US08010819B2

公开(公告)日：2011-08-30

申请号：US12255127

申请日：2008-10-21

申请人： Douglas F. Pastorello ,  Douglas Holberg ,  William Gene Durbin ,  Biranchinath Sahu ,  Golam R. Chowdhury

发明人： Douglas F. Pastorello ,  Douglas Holberg ,  William Gene Durbin ,  Biranchinath Sahu ,  Golam R. Chowdhury

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F1/10

CPC分类号： G06F1/3203 ,  H03K19/0016

摘要： A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.

摘要翻译： 微控制器单元包括用于产生第一控制信号以开始微控制器单元的昏迷模式的处理器。 响应于第一控制信号的控制逻辑在第一电平产生使能信号，并且控制逻辑还响应于第二控制信号，以在第二电平产生使能信号。 电压调节器从输入电压产生调节电压。 电压调节器关闭，以响应于在第一电平的使能信号提供零伏调节电压，并且上电以响应于在第二电平的使能信号提供处于工作电平的调节电压。

公开(公告)号：US20070079148A1

公开(公告)日：2007-04-05

申请号：US11240923

申请日：2005-09-30

申请人： Douglas Pastorello ,  Douglas Holberg ,  William Durbin ,  Biranchinath Sahu ,  Golam Chowdhury

发明人： Douglas Pastorello ,  Douglas Holberg ,  William Durbin ,  Biranchinath Sahu ,  Golam Chowdhury

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  H03K19/0016

摘要： A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.

摘要翻译： 微控制器单元包括用于产生第一控制信号以开始微控制器单元的昏迷模式的处理器。 响应于第一控制信号的控制逻辑在第一电平产生使能信号，并且控制逻辑还响应于第二控制信号，以在第二电平产生使能信号。 电压调节器从输入电压产生调节电压。 电压调节器关闭，以响应于在第一电平的使能信号提供零伏调节电压，并且上电以响应于在第二电平的使能信号提供处于工作电平的调节电压。

公开(公告)号：US20060066392A1

公开(公告)日：2006-03-30

申请号：US10954887

申请日：2004-09-30

申请人： Golam Chowdhury ,  Douglas Holberg

发明人： Golam Chowdhury ,  Douglas Holberg

IPC分类号： H03K5/00

CPC分类号： H03H11/04 ,  H03B5/14 ,  H03F1/342 ,  H03F3/45183 ,  H03F2203/45318 ,  H03F2203/45366 ,  H03L7/0995

摘要： A system and method for providing a tunable GMC filter is disclosed wherein a transconducted element having an attenuator in a feedback loop therewith is allowed to oscillate at a first oscillation frequency. An input to the filter enables tuning of the oscillation frequency to a pre-determined frequency.

摘要翻译： 公开了一种用于提供可调GMC滤波器的系统和方法，其中具有与其反馈回路中的衰减器的跨导元件被允许以第一振荡频率振荡。 滤波器的输入使振荡频率调谐到预定频率。

公开(公告)号：US07504902B2

公开(公告)日：2009-03-17

申请号：US11618581

申请日：2006-12-29

申请人： Douglas Piasecki ,  Douglas Holberg

发明人： Douglas Piasecki ,  Douglas Holberg

IPC分类号： H03L1/04 ,  G06F1/00

CPC分类号： H03K3/0231 ,  H03K3/356113 ,  H03K5/2481

摘要： The integrated system on a chip with LINBUS network communication capabilities includes processing circuitry for performing predefined digital processing functionalities on the chip. A free running clock circuit generates a temperature compensated clock that does not require a synch signal from external to the chip. A LINBUS network communications interface digitally communicates with off-chip LINBUS devices. Communication between said on-chip LINBUS communications interface and the off-chip LINBUS devices is affected without clock recovery. The LINBUS network communication interface has a time base derived from the temperature compensated clock which is independent of any timing information in the input data received during a receive operation. The temperature compensated clock further provides an on-chip time reference for both the processing circuitry and the LINBUS network communications interface.

摘要翻译： 具有LINBUS网络通信能力的芯片上的集成系统包括用于在芯片上执行预定义的数字处理功能的处理电路。 自由运行的时钟电路产生温度补偿时钟，不需要来自芯片外部的同步信号。 LINBUS网络通信接口与片外LINBUS设备进行数字通信。 所述片上LINBUS通信接口和片外LINBUS器件之间的通信不受时钟恢复的影响。 LINBUS网络通信接口具有从温度补偿时钟导出的时基，其独立于在接收操作期间接收的输入数据中的任何定时信息。 温度补偿时钟还为处理电路和LINBUS网络通信接口提供片上时间参考。

公开(公告)号：US20060197847A1

公开(公告)日：2006-09-07

申请号：US11415000

申请日：2006-05-01

申请人： Sandra Johnson ,  Shih-Chung Chao ,  Nadi Itani ,  Caiyi Wang ,  Brannon Harris ,  Ash Prabala ,  Douglas Holberg ,  Alan Hansford ,  Syed Azim ,  David Welland

发明人： Sandra Johnson ,  Shih-Chung Chao ,  Nadi Itani ,  Caiyi Wang ,  Brannon Harris ,  Ash Prabala ,  Douglas Holberg ,  Alan Hansford ,  Syed Azim ,  David Welland

IPC分类号： H04N5/235

CPC分类号： H04N5/3575 ,  H04N5/335 ,  H04N5/361

摘要： An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.

公开(公告)号：US06950047B1

公开(公告)日：2005-09-27

申请号：US10816436

申请日：2004-03-31

申请人： Douglas Piasecki ,  James Dub Austin ,  Douglas Holberg ,  Kenneth Fernald

发明人： Douglas Piasecki ,  James Dub Austin ,  Douglas Holberg ,  Kenneth Fernald

IPC分类号： H03M1/00 ,  H03M1/20 ,  H03M1/68 ,  H03M1/74

CPC分类号： H03M1/68 ,  H03M1/742

摘要： Method and apparatus for combining outputs of multiple DACs for increased bit resolution. A method for providing an increased bit resolution to a data converter operable to convert digital information to analog values. A first current Digital-to-Analog (IDAC) converter is controlled to provide current to a first output node, the first IDAC having a first current step size associated with the Least Significant Bit (LSB) thereof. A second IDAC is controlled to provide current to the first output node, the second IDAC having a second current step size associated with the LSB thereof that is smaller than the first current step size. The combination of the first and second IDACs increases the bit resolution of the first IDAC when driving the first output node with the second IDAC.

摘要翻译： 用于组合多个DAC的输出以提高比特分辨率的方法和装置。 一种用于向可操作以将数字信息转换为模拟值的数据转换器提供增加的位分辨率的方法。 控制第一当前数模（IAC）转换器以向第一输出节点提供电流，第一IDAC具有与其最低有效位（LSB）相关联的第一当前步长。 控制第二IDAC以向第一输出节点提供电流，第二IDAC具有与其LSB的相关联的小于第一当前步长的第二当前步长。 当用第二IDAC驱动第一输出节点时，第一和第二IDAC的组合增加了第一IDAC的位分辨率。

公开(公告)号：US20050206536A1

公开(公告)日：2005-09-22

申请号：US11005700

申请日：2004-12-07

申请人： Douglas Holberg ,  Kenneth Fernald

发明人： Douglas Holberg ,  Kenneth Fernald

IPC分类号： H03K19/173 ,  H03M7/00

CPC分类号： H03K19/1731

摘要： A cross-bar matrix includes a plurality of matrix cells arranged in rows and columns wherein each row of cells is associated with a signal input and each column of cells is associated with a common signal output. An enable input controls whether at least a portion of the cells couple a signal on the associated common signal input to a signal output associated with a cell or couple an LCD signal to a signal output and exclude control of the at least portion of said plurality of cells by the control input.

摘要翻译： 交叉矩阵矩阵包括以行和列排列的多个矩阵单元，其中每行单元与信号输入相关联，并且每列单元与公共信号输出相关联。 使能输入控制是否至少一部分单元将相关联的公共信号输入上的信号耦合到与单元相关联的信号输出或将LCD信号耦合到信号输出，并且排除对所述多个 单元由控制输入。

公开(公告)号：US06922164B1

公开(公告)日：2005-07-26

申请号：US10815416

申请日：2004-03-31

申请人： Douglas Piasecki ,  Douglas Holberg ,  Ka Y. Leung ,  Donald E. Alfano

发明人： Douglas Piasecki ,  Douglas Holberg ,  Ka Y. Leung ,  Donald E. Alfano

IPC分类号： H03M1/34 ,  H03M1/46

CPC分类号： H03M1/462

摘要： SAR analog-to-digital converter with abort function. A method for increasing the throughput of a data converter decision is disclosed. First, a data conversion operation is initiated to convert analog signals on an analog input on a data converter to digital data by sampling the analog signals on the analog signal input and then converting the sampled analog signals to digital data with a predetermined data conversion algorithm in a data conversion operation. The digital output of the data converter is compared to a threshold voltage value. When the output of the data converter is determined by the step of comparing to meet a predetermined relationship relative to the threshold voltage, the data conversion operation is terminated prior to the complete execution of the data conversion operation on the sampled analog signals.

摘要翻译： 具有中止功能的SAR模数转换器。 公开了一种用于增加数据转换器决定的吞吐量的方法。 首先，通过对模拟信号输入上的模拟信号进行采样，然后利用预定的数据转换算法将采样的模拟信号转换成数字数据，开始数据转换操作以将数据转换器上的模拟输入上的模拟信号转换成数字数据 数据转换操作。 将数据转换器的数字输出与阈值电压值进行比较。 当通过比较步骤确定数据转换器的输出以达到相对于阈值电压的预定关系时，在对采样的模拟信号完成数据转换操作之后终止数据转换操作。

公开(公告)号：US07315200B2

公开(公告)日：2008-01-01

申请号：US10816266

申请日：2004-03-31

申请人： Douglas Holberg ,  Ka Y. Leung

发明人： Douglas Holberg ,  Ka Y. Leung

IPC分类号： H04B1/10

CPC分类号： H03M3/484 ,  H03M3/49

摘要： Gain control for delta sigma analog-to-digital converter. A method is disclosed for driving the input of an integrator in a delta-sigma converter having an amplifier with a non-inverting input, an output and a positive input connected to a reference voltage and an integration capacitor connected between the non-inverting input and the output. An input voltage is sampled at a first rate onto an input sampling capacitor and then charge is dumped from the input sampling capacitor to the non-inverting input of the amplifier at a second time and at the first rate. A reference voltage is sampled onto a feedback sampling capacitor at substantially the first rate, and charge stored on the feedback sampling capacitor is dumped to the non-inverting input of the amplifier at a second rate different than the first rate. The amount of time that charge is dumped from the feedback sampling capacitor is controlled to be substantially equal to the amount of time that charge is being dumped from the input sampling capacitor, wherein varying the second rate relative to the first rate changes the gain of delta-sigma converter.

摘要翻译： 增量控制用于Δ-Σ模数转换器。 公开了一种用于驱动积分器的输入的方法，该Δ-Σ转换器具有放大器，其具有连接到参考电压的非反相输入，输出和正输入以及连接在非反相输入和 输出。 输入电压以第一速率被采样到输入采样电容器上，然后在第二时间和第一速率将电荷从输入采样电容器转储到放大器的非反相输入端。 以基本上第一速率将参考电压采样到反馈采样电容器上，并且存储在反馈采样电容器上的电荷以不同于第一速率的第二速率被转储到放大器的非反相输入端。 从反馈采样电容器转储电荷的时间量被控制为基本上等于从输入采样电容器转储电荷的时间量，其中相对于第一速率改变第二速率改变增量 -Σ转换器。