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11.发明授权公开(公告)号：US11211903B1
公开(公告)日：2021-12-28
申请号：US17087643
申请日：2020-11-03
Inventor： Ya-Mien Hsu , Deng-Yao Shih , Yang-Jing Huang
Abstract: An over charge protection method applied to a voltage converter which can operate in a quaternary modulation mode (Q mode) or a ternary modulation mode (T mode). The over charge protection method comprises: (a) determining whether the voltage converter operates in the Q mode or the T mode; and (b) setting a current threshold of the voltage converter to a first over current threshold if the voltage converter operates in the T mode; and (c) setting the current threshold to a second over current threshold if the voltage converter operates in the Q mode, wherein the first current threshold is smaller than the second over current threshold.
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公开(公告)号：US20250060724A1
公开(公告)日：2025-02-20
申请号：US18235361
申请日：2023-08-18
Inventor： Ming-Fu Tsai , Sheng-Hung Hsu
IPC: G05B19/4062
Abstract: An inductor driving device includes multiple switching elements and a control circuit, wherein an inductor is driven according to switching of the multiple switching elements. The control circuit is arranged to generate a control signal for controlling the multiple switching elements. In a first mode, the control signal has a constant frequency. In a second mode, the control circuit adjusts a frequency of the control signal and continuously changes a current direction of the inductor, to generate one of multiple audio signals through the inductor.
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公开(公告)号：US20250060398A1
公开(公告)日：2025-02-20
申请号：US18235356
申请日：2023-08-18
Inventor： Yi-Chou Huang
IPC: G01R27/26
Abstract: A capacitance measurement circuit includes a charge to voltage converter (CVC) that includes at least one first variable capacitor, an excitation signal generation circuit, a differential amplifier, a first switch circuit, and at least one second variable capacitor, wherein a parasitic capacitance from a sensing capacitance sensed by a capacitance sensor is reduced by the at least one first variable capacitor. The excitation signal generation circuit is arranged to generate and connect a first excitation signal to the capacitance sensor, and generate and connect a second excitation signal to the at least one first variable capacitor, wherein the first excitation signal and the second excitation signal are out-of-phase, and a voltage amplitude of the first excitation signal is different from a voltage amplitude of the second excitation signal. The inverting input terminal of the differential amplifier is arranged to receive the sensing capacitance from the capacitance sensor.
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公开(公告)号：US20240356326A1
公开(公告)日：2024-10-24
申请号：US18135935
申请日：2023-04-18
Inventor： Isaac Y. CHEN
CPC classification number: H02H3/08 , H02H1/0007
Abstract: An abnormal current protection device includes an overcurrent protector and a controller, and the overcurrent protector includes a short-circuit detection unit and an overcurrent detection unit. The short-circuit detection unit is configured to detect whether there is a short-circuit event within a period of debounce time of a protection cycle. The overcurrent detection unit is configured to detect whether there is an overcurrent event after the period of debounce time within the protection cycle. The controller is configured to disable a converter when the short-circuit event is detected, and disable a power stage when the overcurrent event is detected.
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公开(公告)号：US20240328853A1
公开(公告)日：2024-10-03
申请号：US18507115
申请日：2023-11-13
Inventor： DAR-CHANG JUANG
CPC classification number: G01J1/44 , G01J1/0228 , H03F3/087 , G01J2001/444 , H03G3/3084
Abstract: An active clamp photoelectric sensing device includes an input terminal, a first output terminal, a current-to-voltage conversion circuit, and an active clamp circuit. The input terminal receives an input current. The first output terminal outputs a first output voltage. The current-to-voltage conversion circuit is coupled between the input terminal and the first output terminal, and is used to discharge and lower potentials of the input terminal and the first output terminal to a first set voltage according to the state of a reset signal, or is used to gradually increase the first output voltage to a second set voltage. The active clamping circuit is coupled to the current-to-voltage conversion circuit, and is used to clamp the upper limit of the first output voltage to the second set voltage.
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Patent Agency Ranking
公开(公告)号：US20240178796A1
公开(公告)日：2024-05-30
申请号：US18071581
申请日：2022-11-29
Inventor： Isaac Y. Chen
CPC classification number: H03F1/0205 , H03F3/217 , H03F2200/03
Abstract: An audio amplifier includes a plurality of power stages, a driving circuit, and a power stage control circuit. The driving circuit is arranged to drive the power stages. The power stage control circuit includes a feedback circuit and a control circuit. The feedback circuit is coupled to the power stages, and is arranged to generate a feedback signal according to at least one detection input, wherein the at least one detection input includes at least one of a power, a voltage signal corresponding to a switching time of the power stages, and a voltage signal corresponding to a switching frequency of the power stages. The control circuit is coupled between the feedback circuit and the power stages, and is arranged to generate a control signal according to the feedback signal, wherein the control signal is arranged to dynamically control a number of turned-on power stages in the power stages.
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公开(公告)号：US20240133934A1
公开(公告)日：2024-04-25
申请号：US17964847
申请日：2022-10-12
Inventor： Yi-Chou Huang
CPC classification number: G01R27/2605 , H03F3/45475 , H03M3/30 , H03F2200/213 , H03F2200/271 , H03F2203/45156
Abstract: A capacitance measure circuit includes a charge to voltage converter (CVC), and the CVC includes an excitation signal generation circuit that is arranged to generate and connect an excitation signal to a first terminal of a capacitance sensor, a differential amplifier, a first switch circuit, and at least one first variable capacitor. The inverting input terminal of the differential amplifier is arranged to receive a sensing capacitance value from a second terminal of the capacitance sensor. The first switch circuit is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier, and is connected in parallel with the at least one first variable capacitor at the inverting input terminal and the non-inverting output terminal of the differential amplifier.
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公开(公告)号：US11955163B2
公开(公告)日：2024-04-09
申请号：US17875449
申请日：2022-07-28
Inventor： Po-Hsun Wu , Jen-Shou Hsu
IPC: G11C11/408
CPC classification number: G11C11/4087
Abstract: Method and circuit for adaptive column-select line signal generation for a memory device are provided. The method comprises the following steps. A first signal is generated in response to a memory access command. A second signal is generated according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is asserted, the first candidate signal is asserted when a configurable time interval with respect to a parameter from a register set elapses and the second candidate signal is asserted when a specified time interval elapses, and the selected candidate signal is asserted before a remaining part of the candidate signals after the first signal is asserted. A column-select line signal is generated according to the first signal and the second signal.
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公开(公告)号：US20240038293A1
公开(公告)日：2024-02-01
申请号：US17875449
申请日：2022-07-28
Inventor： PO-HSUN WU , JEN-SHOU HSU
IPC: G11C11/408
CPC classification number: G11C11/4087
Abstract: Method and circuit for adaptive column-select line signal generation for a memory device are provided. The method comprises the following steps. A first signal is generated in response to a memory access command. A second signal is generated according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is asserted, the first candidate signal is asserted when a configurable time interval with respect to a parameter from a register set elapses and the second candidate signal is asserted when a specified time interval elapses, and the selected candidate signal is asserted before a remaining part of the candidate signals after the first signal is asserted. A column-select line signal is generated according to the first signal and the second signal.
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公开(公告)号：US20230421143A1
公开(公告)日：2023-12-28
申请号：US17847225
申请日：2022-06-23
Inventor： Shu-Han Nien
CPC classification number: H03K5/135 , H03K5/2427 , H03K5/2418 , H03K2005/00176
Abstract: An input clock buffer, comprising: a first capacitor; a second capacitor; a first amplifier, configured to generate a first output signal, comprising input terminals coupled to the first capacitor and the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal; a second amplifier, configured to generate a second output signal according to the differential input signal; a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.
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