公开(公告)号：US11689190B2

公开(公告)日：2023-06-27

申请号：US17973740

申请日：2022-10-26

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Yu-Hao Liu ,  Sheng-Hua Chen ,  Cheng-Hsing Chien

IPC: H03K3/356 ,  H03K3/012 ,  H03K3/037

CPC classification number: H03K3/356104 ,  H03K3/012 ,  H03K3/037

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

公开(公告)号：US20230077161A1

公开(公告)日：2023-03-09

申请号：US17692230

申请日：2022-03-11

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Yi-Che TSAI

IPC: H04L25/14 ,  H04L25/02 ,  H04L25/06

Abstract: A de-skew circuit, a de-skew method and a receiver are provided. The de-skew circuit includes N data synchronization circuits and a controller. An nth data synchronization circuit among the N data synchronization circuits includes an nth command detector and an nth buffer. The nth command detector changes an nth command detection signal when an nth input data stream satisfies a single channel condition. The nth buffer stores the nth input data stream in response to a voltage change of the nth command detection signal. The controller receives the nth command detection signal and changes a pop signal when a global channel condition is satisfied. The nth buffer outputs an nth timing-aligned data stream in response to a voltage change of the pop signal.

公开(公告)号：US20220182044A1

公开(公告)日：2022-06-09

申请号：US17184640

申请日：2021-02-25

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Yu-Hao LIU ,  Sheng-Hua CHEN ,  Cheng-Hsing CHIEN

IPC: H03K3/037

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

公开(公告)号：US11245408B2

公开(公告)日：2022-02-08

申请号：US17151673

申请日：2021-01-19

Applicant: FARADAY TECHNOLOGY CORPORATION ,  Faraday Technology Corp.

Inventor： Feng Xu ,  Chih-Yuan Hung ,  Meng Zhao

IPC: H03M1/06 ,  H03M1/00

Abstract: A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed.

公开(公告)号：US11023023B2

公开(公告)日：2021-06-01

申请号：US16709021

申请日：2019-12-10

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Kun-Hua Huang ,  Chang-Chin Chung ,  Kun-Chih Chen

IPC: G06F1/24 ,  G06F13/42 ,  G06F1/04 ,  H03K19/20

Abstract: A start-and-stop detecting apparatus for an I3C bus is provided. The start-and-stop detecting apparatus is connected with a serial data line and a serial clock line. The start-and-stop detecting apparatus includes a first start detecting circuit, a second start detecting circuit and a first OR gate. The first start detecting circuit receives a data signal, a clock signal and a reset signal, and generates a first control signal and a first output signal. The second start detecting circuit receives the data signal, the clock signal, the reset signal and the first control signal, and generates a second output signal. A first input terminal of the first OR gate receives the first output signal. A second input terminal of the first OR gate receives the second output signal. An output terminal of the first OR gate generates a start signal.

公开(公告)号：US20200272536A1

公开(公告)日：2020-08-27

申请号：US16429618

申请日：2019-06-03

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Shan-Tai CHEN ,  Jian-Guo CHEN ,  Chun-Yuan LAI

IPC: G06F11/10 ,  G06F9/4401 ,  G06F12/02 ,  H04L9/06

Abstract: A method of executing an initial program load in an electronic device is provided. The electronic device includes a chip. The chip is connected with a storage device. The method includes the following steps. First, checking data and a characteristic value are read from the storage device. Then, an algorithm parameter is acquired from the checking data. Then, the checking data and the characteristic value are verified according to a specified checking algorithm and the algorithm parameter. If a result of the specified checking algorithm passes, a boot code is executed. If the result of the specified checking algorithm fails, a notification signal is issued.

公开(公告)号：US09484085B1

公开(公告)日：2016-11-01

申请号：US15098329

申请日：2016-04-14

Applicant: Faraday Technology Corporation ,  Faraday Technology Corp.

Inventor： Zhao-Yong Zhang ,  Kun-Ti Lee

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A static memory apparatus and a static memory cell thereof are provided. The static memory cell includes a data latch circuit, a data write-in circuit and a data read-out circuit. The data latch circuit has a first tristate output inverting circuit and a second tristate output inverting circuit. The data write-in circuit provides a first reference voltage to a power receiving terminal of a selected tristate output inverting circuit which is one of the first and second tristate output inverting circuits, and provides a second reference voltage to an input terminal of the selected tristate output inverting circuit during a data write-in time period. The data read-out circuit generates read-out data according to a voltage at an output terminal of the second tristate output inverting circuit and the second reference voltage during a data read-out time period.

Abstract translation: 提供了一种静态存储装置及其静态存储单元。 静态存储单元包括数据锁存电路，数据写入电路和数据读出电路。 数据锁存电路具有第一三态输出反相电路和第二三态输出反相电路。 数据写入电路向作为第一和第二三态输出反相电路之一的所选三态输出反相电路的功率接收端提供第一参考电压，并向所选三态输入端的输入端提供第二参考电压 在数据写入期间输出反相电路。 数据读出电路根据数据读出期间的第二三态输出反相电路的输出端的电压和第二基准电压来生成读出数据。

公开(公告)号：US09298660B2

公开(公告)日：2016-03-29

申请号：US13727796

申请日：2012-12-27

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Liang-Ting Lin

IPC: G06F13/40

CPC classification number: G06F13/4059 ,  G06F2213/0042

Abstract: A super speed USB hub includes an upstream port, a plurality of device ports, a transaction dispatching unit, a downstream buffer, a hub local packet parser, a traffic control unit, and a forwarding unit. The transaction dispatching unit is used for receiving a plurality of packets from a USB host, wherein the plurality of packets comprise a plurality of downstream packets and a hub command packet. If the hub command packet contains a traffic management command, the hub local packet parser generates a selected target and a control mode according to the traffic management command. The traffic control unit is used for managing a downstream packet corresponding to the selected target among the plurality of downstream packets in the downstream buffer according to the selected target and the control mode.

Abstract translation: 超速USB集线器包括上游端口，多个设备端口，事务调度单元，下游缓冲器，集线器本地分组解析器，业务控制单元和转发单元。 交易调度单元用于从USB主机接收多个分组，其中多个分组包括多个下行分组和集线器命令分组。 如果集线器命令包包含流量管理命令，则集线器本地数据包解析器根据流量管理命令生成所选目标和控制模式。 流量控制单元用于根据所选择的目标和控制模式来管理下游缓冲器中的多个下游分组中对应于所选择的目标的下行分组。

公开(公告)号：US20140149628A1

公开(公告)日：2014-05-29

申请号：US13727796

申请日：2012-12-27

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Liang-Ting Lin

IPC: G06F13/40

CPC classification number: G06F13/4059 ,  G06F2213/0042

Abstract: A super speed USB hub includes an upstream port, a plurality of device ports, a transaction dispatching unit, a downstream buffer, a hub local packet parser, a traffic control unit, and a forwarding unit. The transaction dispatching unit is used for receiving a plurality of packets from a USB hot, wherein the plurality of packets comprise a plurality of downstream packets and a hub command packet. If the hub command packet contains a traffic management command, the hub local packet parser generates a selected target and a control mode according to the traffic management command. The traffic control unit is used for managing a downstream packet corresponding to the selected target among the plurality of downstream packets in the downstream buffer according to the selected target and the control mode.

Abstract translation: 超速USB集线器包括上游端口，多个设备端口，事务调度单元，下游缓冲器，集线器本地分组解析器，业务控制单元和转发单元。 交易调度单元用于从USB热接收多个分组，其中所述多个分组包括多个下行分组和集线器命令分组。 如果集线器命令包包含流量管理命令，则集线器本地数据包解析器根据流量管理命令生成所选目标和控制模式。 流量控制单元用于根据所选择的目标和控制模式来管理下游缓冲器中的多个下游分组中对应于所选择的目标的下行分组。

公开(公告)号：US12124618B2

公开(公告)日：2024-10-22

申请号：US17899653

申请日：2022-08-31

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Chun-Yuan Lai

IPC: G06F21/72 ,  G06F21/57 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14

CPC classification number: G06F21/72 ,  G06F21/575 ,  H04L9/0618 ,  H04L9/0894 ,  H04L9/14 ,  G06F2221/034

Abstract: An SoC architecture includes a non-volatile memory and an SoC chip. The SoC chip is connected with the non-volatile memory. The SoC chip includes a central processing unit, a volatile memory, a system bus, an on-the-fly decryption circuit, a memory interface, a timer and a key bank. The on-the-fly decryption circuit is connected with the key bank. The on-the-fly decryption circuit performs an encryption operation or a decryption operation according to plural keys in the key bank. After the SoC architecture is powered on, if the timer is not disabled and the timer has counted time for a specified time period, the central processing unit is subjected to a warm reset, and a storage format in the non-volatile memory is changed from an initial format to an operation format by the central processing unit.