公开(公告)号：US20140002286A1

公开(公告)日：2014-01-02

申请号：US13539658

申请日：2012-07-02

申请人： Peter BOGNER ,  Franz KUTTNER

发明人： Peter BOGNER ,  Franz KUTTNER

IPC分类号： H03M1/38

CPC分类号： H03M1/1225 ,  H03M1/1205

摘要： Representative implementations of devices and techniques provide analog to digital conversion of multiple parallel analog inputs. An input interface is arranged to organize the parallel analog inputs and an analog-to-digital converter (ADC) is arranged to sequentially convert the multiple parallel analog inputs to digital results.

摘要翻译： 器件和技术的代表性实现提供了多个并行模拟输入的模数转换。 布置了输入接口来组织并行模拟输入，并且设置模数转换器（ADC）以将多个并行模拟输入顺序地转换成数字结果。

公开(公告)号：US08111182B2

公开(公告)日：2012-02-07

申请号：US12578301

申请日：2009-10-13

申请人： Franz Kuttner

发明人： Franz Kuttner

IPC分类号： H03M1/66

CPC分类号： H03M1/685 ,  H03M1/747

摘要： In some embodiments, digital to analog converters are provided which comprise a plurality of cells. Each cell comprises a mixer and coupling circuitry to selectively couple a local oscillator signal to said mixer.

摘要翻译： 在一些实施例中，提供了包括多个单元的数模转换器。 每个单元包括用于选择性地将本地振荡器信号耦合到所述混频器的混频器和耦合电路。

公开(公告)号：US07640002B2

公开(公告)日：2009-12-29

申请号：US11521326

申请日：2006-09-14

申请人： Franz Kuttner

发明人： Franz Kuttner

IPC分类号： H04B1/26 ,  H04B1/28

CPC分类号： H03F3/45237 ,  H03F3/19 ,  H03F3/45183 ,  H03F3/45197 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45644 ,  H03F2203/45648

摘要： An RF amplifier for amplifying a composite RF signal includes a first RF signal and a second RF signal. The amplifier includes a first amplifying stage for providing a first amplified signal a second amplifying stage for providing a second amplified signal, a third amplifying stage for providing a third amplified signal and a fourth amplifying stage for providing a fourth amplified signal, the fourth amplifying stage being arranged after the third amplifying stage. The respective amplified signals are summed up to obtain amplified RF signals.

摘要翻译： 用于放大复合RF信号的RF放大器包括第一RF信号和第二RF信号。 放大器包括用于提供第一放大信号的第一放大级，用于提供第二放大信号的第二放大级，用于提供第三放大信号的第三放大级和用于提供第四放大信号的第四放大级，第四放大级 被布置在第三放大级之后。 将相应的放大信号相加以获得放大的RF信号。

公开(公告)号：US07474243B1

公开(公告)日：2009-01-06

申请号：US11854849

申请日：2007-09-13

申请人： Franz Kuttner

发明人： Franz Kuttner

IPC分类号： H03M1/66

CPC分类号： H03M1/0863 ,  H03M1/685 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

摘要： A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a first switch, a second switch, and a third switch. The first switch is configured to latch a bit in a series of bits to provide a latched bit. The second switch is configured to conduct based on the latched bit. The third switch is configured to conduct based on the latched bit and a next bit in the series of bits. The next bit follows the latched bit in the series of bits.

摘要翻译： 公开了一种半导体器件。 在一个实施例中，半导体器件包括第一开关，第二开关和第三开关。 第一开关被配置为锁存一系列比特以提供锁存比特。 第二开关被配置为基于锁存位进行。 第三开关被配置为基于锁存位和一系列位中的下一位进行。 接下来的位跟随该系列位中的锁存位。

公开(公告)号：US07342530B2

公开(公告)日：2008-03-11

申请号：US11477308

申请日：2006-06-29

申请人： Franz Kuttner

发明人： Franz Kuttner

IPC分类号： H03M1/34

CPC分类号： H03M1/403

摘要： A successive approximation analog/digital converter converting an analog input signal into a digital output value by means of a plurality of successive conversion cycles, comprises at least one first input for injecting an analog input signal, a controllable capacitive network which is connected downstream of the first input and which is divided into at least two capacitive subnetworks and, at least two parallel-connected and parallel-operating comparators for defining a number of comparator thresholds which corresponds to the number of parallel comparators. The comparators are respectively connected downstream of one of the capacitive subnetworks and the comparators output a corresponding number of digital intermediate signals on the basis of the comparisons in the comparators. The analog/digital converter further comprises a register set by the intermediate signals. The register buffer-stores digital intermediate values for the respective intermediate signals and produces control signals for actuating the capacitive subnetworks in response to the content of the intermediate signals.

摘要翻译： 通过多个连续转换周期将模拟输入信号转换为数字输出值的逐次逼近模拟/数字转换器包括至少一个用于注入模拟输入信号的第一输入端，连接在下游的可控电容网络 第一输入并且被分成至少两个电容子网络，以及至少两个并联和并联操作的比较器，用于定义对应于并行比较器的数量的多个比较器阈值。 比较器分别连接在一个电容子网的下游，并且比较器基于比较器中的比较来输出相应数量的数字中间信号。 模拟/数字转换器还包括由中间信号设置的寄存器。 寄存器缓冲器存储用于各个中间信号的数字中间值，并且响应于中间信号的内容产生用于启动电容子网的控制信号。

公开(公告)号：US07307567B2

公开(公告)日：2007-12-11

申请号：US10564312

申请日：2004-07-07

申请人： Franz Kuttner

发明人： Franz Kuttner

IPC分类号： H03M1/66

CPC分类号： H03M1/066 ,  H03M1/685 ,  H03M3/502

摘要： The present invention provides a digital-analog converter having: a DEM logic device (10) for generating at least two digital output data items (13, 14) from the digital input data (11) on the basis of a predetermined algorithm to determine an initial cell and a final cell in the array arrangement (22), between which there are situated cells (24) with energy sources (30) to be activated; a decoder device (16) for decoding the at least two digital output data items (13, 14) from the DEM device (10) into actuation signals (17, 17′, 18, 18′, 19, 19′ 20, 20′, 21, 21′) in order to activate the cells (24) which are to be activated; and an array arrangement (22) of cells (23) for outputting at least one quantized analog signal (25, 25′) on the basis of the actuation signals (17, 17′, 18, 18′, 19, 19′ 20, 20′, 21, 21′). The present invention likewise provides a method for digital-analog conversion.

摘要翻译： 本发明提供了一种数模转换器，具有：DEM逻辑器件（10），用于根据预定算法从数字输入数据（11）生成至少两个数字输出数据项（13,14），以确定 初始单元和阵列布置（22）中的最终单元，其间具有要被激活的能量源（30）的单元（24）; 解码器装置（16），用于将来自DEM装置（10）的至少两个数字输出数据项（13,14）解码为致动信号（17,17'，18,18'，19,19'20,20' ，21,21'），以激活待激活的细胞（24）; 以及用于基于所述致动信号（17,17'，18,18'，19,19'，20'）输出至少一个量化的模拟信号（25,25'）的单元（23）的阵列布置（22） 20'，21，21'）。 本发明同样提供了一种用于数模转换的方法。

公开(公告)号：US5646622A

公开(公告)日：1997-07-08

申请号：US631804

申请日：1996-04-11

申请人： Franz Kuttner

发明人： Franz Kuttner

IPC分类号： H03M1/18 ,  H03M1/46 ,  H03M1/80 ,  H03M1/12

CPC分类号： H03M1/468 ,  H03M1/804

摘要： An analog/digital converter includes a comparator with two inputs and one output. One capacitor is connected between a reference potential and one of the inputs of the comparator. A coupling element is connected between a node point and the other of the inputs of the comparator. N further capacitors each have two terminals. One terminal of each of the further capacitors is connected to the node point. N individually controllable reversing switches each connect the other terminal of a respective one of the further capacitors to an input potential, a first reference potential or a second reference potential. A control device is connected to the output of the comparator and to the reversing switches to control the reversing switches for connecting at least some of the further capacitors to the input potential and for connecting each of the remainder of the further capacitors to one of the two reference potentials, during a transfer phase. The reversing switches include at least some reversing switches having switch positions alternating continuously among one another between the reference potentials until an appearance of a signal change at the output of the comparator, and remaining reversing switches each connecting a respective one of the capacitors to a respective one of the two reference potentials, during a conversion phase.

摘要翻译： 模拟/数字转换器包括具有两个输入和一个输出的比较器。 一个电容器连接在参考电位和比较器的一个输入端之间。 耦合元件连接在比较器的节点和另一个输入端之间。 另外N个电容器有两个端子。 每个另外的电容器的一个端子连接到节点。 N个可独立控制的反向开关各自将另外一个电容器的另一个端子连接到输入电位，第一参考电位或第二参考电位。 控制装置连接到比较器的输出端和反向开关，以控制反向开关，用于将至少一些其它电容器连接到输入电位，并将剩余的其余电容器中的每一个连接到两个电容器中的一个 参考电位，在转移阶段。 反转开关包括至少一些反转开关，其具有在参考电位之间彼此连续交替的开关位置，直到在比较器的输出处出现信号变化，以及将各个电容器连接到相应的电容器的剩余反向开关 在转换阶段，两个参考电位之一。

公开(公告)号：US20180091338A1

公开(公告)日：2018-03-29

申请号：US15274721

申请日：2016-09-23

申请人： Christian Mayer ,  Franz Kuttner

发明人： Christian Mayer ,  Franz Kuttner

IPC分类号： H04L27/08 ,  H04B1/04 ,  H04B1/00

CPC分类号： H04L27/08 ,  H04B1/0042 ,  H04B1/04 ,  H04L27/2614

摘要： Disclosed herein is an apparatus and methodology for reducing peak-to-average-power ratio (PAPR) for IQ radio frequency digital-to-analog converter (RFDAC). Processing circuitry may be configured to generate a digital signal comprising an in-phase (I) signal component and a quadrature (Q) signal component having a peak-to-average-power-ratio (PAPR). The processing circuitry may determine the I signal component and the Q signal component are higher than a predetermined threshold value, and limit the I signal component and the Q signal component to be less than or equal to the predetermined threshold value. The processing circuitry may rotate the signal components to generate rotated signal components to reduce the PAPR based on the I and Q signal components having less than or equal to the predetermined threshold value, and may generate an output radio frequency (RF) signal based on the rotated signal components.

公开(公告)号：US20130307615A1

公开(公告)日：2013-11-21

申请号：US13471839

申请日：2012-05-15

申请人： Franz Kuttner

发明人： Franz Kuttner

IPC分类号： H03G1/00

CPC分类号： H02M3/158 ,  H02M3/157 ,  H03F1/0227 ,  H03F1/025

摘要： Embodiments provide a DC-DC converter (DC-DC=direct current to direct current) for envelope tracking. The DC-DC converter includes a digital control stage and a driving stage. The digital control stage is configured to provide a digital control signal based on digital information describing an amplitude of a digital baseband transmit signal. The driving stage is configured to provide a supply voltage for an RF amplifier (RF=radio frequency) based on the digital control signal.

公开(公告)号：US08228094B2

公开(公告)日：2012-07-24

申请号：US12538946

申请日：2009-08-11

申请人： Franz Kuttner

发明人： Franz Kuttner

IPC分类号： H03K5/22

CPC分类号： H03K5/2481

摘要： This disclosure relates to permuting transistors to compensate for offsets generated by transient variations of the transistors' parameters.

摘要翻译： 本公开涉及置换晶体管以补偿由晶体管参数的瞬态变化产生的偏移。