公开(公告)号：US07821315B2

公开(公告)日：2010-10-26

申请号：US11962689

申请日：2007-12-21

Applicant: Frederic Bossu ,  Anthony Francis Segoria

Inventor： Frederic Bossu ,  Anthony Francis Segoria

IPC: H03K3/017 ,  H03K5/04 ,  H03K7/08

CPC classification number: H03K3/017 ,  H03K5/1565

Abstract: Techniques are disclosed for adjusting and programming the duty cycle of a signal generated by a circuit. In an embodiment, parallel transistors are coupled between a NAND gate and a supply voltage. Selectively enabling the parallel transistors adjusts the switching point of the NAND gate, thereby allowing control of the pulse width of the output signal. In an alternative embodiment, the size of the PMOS versus the NMOS transistors in the NAND gate is selectively varied to achieve the same effect. Further disclosed are applications of the techniques to calibrating the receiver to minimize measured second-order inter-modulation products and/or residual sideband.

Abstract translation: 公开了用于调整和编程由电路产生的信号的占空比的技术。 在一个实施例中，并联晶体管耦合在NAND门和电源电压之间。 选择性地使并行晶体管调节NAND门的切换点，从而允许控制输出信号的脉冲宽度。 在替代实施例中，PMOS与NMOS门中的NMOS晶体管的尺寸有选择地变化以达到相同的效果。 进一步公开的是用于校准接收机以最小化测量的二阶互调产物和/或残留边带的技术的应用。

公开(公告)号：US20090111414A1

公开(公告)日：2009-04-30

申请号：US11955201

申请日：2007-12-12

Applicant: Gurkanwal Singh Sahota ,  Frederic Bossu ,  Ojas M. Choksi

Inventor： Gurkanwal Singh Sahota ,  Frederic Bossu ,  Ojas M. Choksi

IPC: H04B1/16

CPC classification number: H03D7/1441 ,  H03D7/165 ,  H03D7/166 ,  H03D2200/0084 ,  H03D2200/009

Abstract: Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an embodiment, LO buffer and/or mixer size may be increased when a receiver operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver operates in a low gain mode. In an embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific embodiments of LO buffers and mixers having adjustable size are disclosed.

Abstract translation: 公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。 在一个实施例中，当接收机以高增益模式工作时，可以增加LO缓冲器和/或混频器的大小，而当接收器以低增益模式工作时，可以减小LO缓冲器和/或混频器的大小。 在一个实施例中，LO缓冲器和混合器尺寸在锁定步骤中增加和减小。 公开了具有可调节尺寸的LO缓冲器和混合器的具体实施例的电路拓扑和控制方案。

公开(公告)号：US20050195034A1

公开(公告)日：2005-09-08

申请号：US11025848

申请日：2004-12-29

Applicant: Jean-Charles Grasset ,  Frederic Bossu

Inventor： Jean-Charles Grasset ,  Frederic Bossu

IPC: H03G1/04 ,  H03G7/06 ,  H03F3/45

CPC classification number: H03G1/04 ,  H03G7/06

Abstract: Attenuation cell comprising first and second differential pairs of bipolar transistors. A gain control device applies a voltage VA-VB between the bases of both differential pairs and comprises a set of three diodes in which a current IA, a current IB and the sum IA+IB of both preceding currents flow, respectively. The two diodes seeing current IB and IA+IB generate a voltage, respectively VB and VC, and the difference between these two voltages is used to generate a value Iz used in a control loop. A desired value Vct is transformed into information Ix, then into information Iy proportional to absolute temperature T, and an error amplifier uses information Iy-Iz and generates currents IA and IB by minimizing this difference.

Abstract translation: 衰减单元包括第一和第二差分双极晶体管对。 增益控制装置在两个差分对的基极之间施加电压VA-VB，并且包括一组三个二极管，其中电流IA，电流IB和前两个电流的和IA + IB分别流动。 看到电流IB和IA + IB的两个二极管分别产生VB和VC的电压，并且使用这两个电压之间的差来产生在控制回路中使用的值Iz。 期望值Vct被转换成信息Ix，然后转换成与绝对温度T成比例的信息Iy，误差放大器使用信息Iy-Iz，并通过最小化该差来产生电流IA和IB。

公开(公告)号：US10044381B2

公开(公告)日：2018-08-07

申请号：US13584273

申请日：2012-08-13

Applicant: Mark Vernon Lane ,  Chang-Ho Lee ,  Christian Holenstein ,  Mahim Ranjan ,  Praveen-Kumar Sampath ,  Frederic Bossu ,  Sumit Verma ,  Wesley Alan Sampson

Inventor： Mark Vernon Lane ,  Chang-Ho Lee ,  Christian Holenstein ,  Mahim Ranjan ,  Praveen-Kumar Sampath ,  Frederic Bossu ,  Sumit Verma ,  Wesley Alan Sampson

IPC: H04B1/04

Abstract: Techniques for using a narrow filter located before a power amplifier to reduce interference in an adjacent frequency band are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes the narrow filter and the power amplifier. The narrow filter is for a first frequency band (e.g., Band 40) and has a first bandwidth that is more narrow than the first frequency band. The narrow filter receives and filters an input radio frequency (RF) signal and provides a filtered RF signal. The power amplifier receives and amplifies the filtered RF signal and provides an amplified RF signal. The apparatus may further include a full filter for the first frequency band and located after the power amplifier. The full filter receives and filters the amplified RF signal and provides an output RF signal when it is selected for use.

公开(公告)号：US08791740B2

公开(公告)日：2014-07-29

申请号：US12724337

申请日：2010-03-15

Applicant: Dongjiang Qiao ,  Bhushan S. Asuri ,  Junxiong Deng ,  Frederic Bossu

Inventor： Dongjiang Qiao ,  Bhushan S. Asuri ,  Junxiong Deng ,  Frederic Bossu

IPC: H03K3/289

CPC classification number: H04B1/408 ,  H03B19/00 ,  H03L7/0812 ,  H04B1/109

Abstract: A method for reducing average current consumption in a local oscillator (LO) path is disclosed. An LO signal is received at a master frequency divider and a slave frequency divider. Output from the master frequency divider is mixed with an input signal to produce a first mixed output. Output from the slave frequency divider is mixed with the input signal to produce a second mixed output. The second mixed output is forced to be in phase with the first mixed output.

Abstract translation: 公开了一种用于降低本地振荡器（LO）路径中的平均电流消耗的方法。 在主分频器和从分频器处接收LO信号。 主分频器的输出与输入信号混合，产生第一个混合输出。 来自从分频器的输出与输入信号混合，产生第二个混合输出。 第二个混合输出被强制与第一个混合输出同相。

公开(公告)号：US08098085B2

公开(公告)日：2012-01-17

申请号：US12436265

申请日：2009-05-06

Applicant: Kevin H. Wang ,  Saru Palakurty ,  Frederic Bossu

Inventor： Kevin H. Wang ,  Saru Palakurty ,  Frederic Bossu

IPC: H03D13/00

CPC classification number: G04F10/005

Abstract: A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.

Abstract translation: 描述具有小于一个逆变器延迟的精细分辨率的时间 - 数字转换器（TDC）。 在示例性设计中，TDC包括第一和第二延迟路径，延迟单元和相位计算单元。 第一延迟路径接收第一输入信号和第一参考信号并提供第一输出。 第二延迟路径接收第二输入信号和第二参考信号并提供第二输出。 延迟单元相对于第一输入信号延迟第二输入信号或相对于第一参考信号延迟第二参考信号，例如延迟半个逆变器延迟。 相位计算单元接收第一和第二输出，并且在输入信号和参考信号之间提供相位差。 可以执行校准以获得第一和第二延迟路径的精确定时。

公开(公告)号：US20090221235A1

公开(公告)日：2009-09-03

申请号：US12366441

申请日：2009-02-05

Applicant: Steven C. Ciccarelli ,  Frederic Bossu ,  Vladimir Aparin ,  Kevin H. Wang

Inventor： Steven C. Ciccarelli ,  Frederic Bossu ,  Vladimir Aparin ,  Kevin H. Wang

IPC: H03D3/24 ,  H04B7/00 ,  H04B17/00 ,  H04M1/00

CPC classification number: H03L7/1974

Abstract: Within a receiver, the frequency of a comparison reference clock signal supplied to a fractional-N Phase-Locked Loop (PLL) is dynamically changed such that undesirable reciprocal mixing of reference spurs with known jammers (for example, transmit leakage) is minimized. As the transmit channel changes within a band, and as the transmit leakage frequency changes, a circuit changes the frequency of the comparison reference clock signal such that reference spurs generated by the PLL are moved in frequency so that they do not reciprocally mix with transmitter leakage in undesirable ways. In a second aspect, the PLL is operable either as an integer-N PLL or a fractional-N PLL. In low total receive power situations, the PLL operates as an integer-N PLL to reduce receiver susceptibility to fractional-N spurs. In a third aspect, jammer detect information is used to determine the comparison reference clock signal frequency.

Abstract translation: 在接收机内，提供给分数N锁相环（PLL）的比较参考时钟信号的频率被动态地改变，使得具有已知干扰的参考杂波（例如，传输泄漏）的不期望的相互混合被最小化。 当发射信道在频带内变化时，并且随着发射泄漏频率的变化，电路改变比较参考时钟信号的频率，使得PLL产生的参考杂波频率移动，使得它们不与发射机泄漏相互混合 以不良的方式。 在第二方面，PLL可以作为整数N个PLL或分数N PLL来操作。 在低总接收功率情况下，PLL作为整数N PLL进行操作，以减少接收机对分数N个杂散的敏感性。 在第三方面，使用干扰检测信息来确定比较参考时钟信号频率。

公开(公告)号：US20090154595A1

公开(公告)日：2009-06-18

申请号：US12259178

申请日：2008-10-27

Applicant: Ojas M. Choksi ,  Frederic Bossu

Inventor： Ojas M. Choksi ,  Frederic Bossu

IPC: H04L27/00

CPC classification number: H04L5/1461 ,  H03D3/009 ,  H03M1/1019 ,  H03M1/66 ,  H04L27/0014 ,  H04L2027/0016 ,  H04L2027/0018 ,  H04L2027/0024

Abstract: Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed.

Abstract translation: 提供了用于减少通信发射机或接收机的同相（I）和正交（Q）信道之间的失配的技术。 在示例性实施例中，施加单独的电压以在I通道的混频器中与Q通道的混频器偏置晶体管的栅极或体积。 在另一个示例性实施例中，施加单独的电压以偏置与每个通道相关联的跨阻抗放大器的共模参考电压。 还提供了用于导出偏置电压以最小化接收或发射信号中测量的残留边带或者优化接收或发射信号的其它参数的技术。 还公开了使用双向和单向电流数模转换器（DAC）产生单独偏置电压的技术。

公开(公告)号：US09300420B2

公开(公告)日：2016-03-29

申请号：US13609532

申请日：2012-09-11

Applicant: Li-Chung Chang ,  Prasad Srinivasa Siva Gudem ,  Frederic Bossu ,  Christian Holenstein

Inventor： Li-Chung Chang ,  Prasad Srinivasa Siva Gudem ,  Frederic Bossu ,  Christian Holenstein

IPC: H04J3/02 ,  H04J3/00 ,  H03F3/72 ,  H04B1/00

CPC classification number: H04J3/00 ,  H03F3/72 ,  H04B1/0064 ,  H04B1/0071

Abstract: A receiver architecture for carrier aggregation is disclosed. In an exemplary design, an apparatus (e.g., a wireless device, a circuit module, etc.) includes a plurality of low noise amplifiers (LNAs), a plurality of switches, and at least one downconverter. The LNAs receive and amplify at least one input radio frequency (RF) signal and provide at least one amplified RF signal. The switches are coupled to the outputs of the plurality of LNAs. The at least one downconverter is coupled to the plurality of switches, downconverts the at least one amplified RF signal, and provides at least one downconverted signal. The switches reduce the number of downconverters needed to support reception of transmissions on multiple sets of carriers via multiple receive antennas. The LNAs and the switches may be implemented on at least one front-end module or a back-end module. The downconverter(s) are implemented on the back-end module.

Abstract translation: 公开了用于载波聚合的接收机架构。 在示例性设计中，装置（例如，无线装置，电路模块等）包括多个低噪声放大器（LNA），多个开关和至少一个下变频器。 LNA接收和放大至少一个输入射频（RF）信号并提供至少一个放大的RF信号。 开关耦合到多个LNA的输出端。 所述至少一个下变频器耦合到所述多个开关，对所述至少一个放大的RF信号进行下变频，并提供至少一个下变频信号。 交换机减少了通过多个接收天线支持在多组载波上接收传输所需的下变频器的数量。 LNA和交换机可以在至少一个前端模块或后端模块上实现。 下变频器在后端模块上实现。

公开(公告)号：US09287886B2

公开(公告)日：2016-03-15

申请号：US12366441

申请日：2009-02-05

Applicant: Steven C. Ciccarelli ,  Frederic Bossu ,  Vladimir Aparin ,  Kevin H. Wang

Inventor： Steven C. Ciccarelli ,  Frederic Bossu ,  Vladimir Aparin ,  Kevin H. Wang

IPC: H04B1/40 ,  H03L7/197

CPC classification number: H03L7/1974

Abstract: Within a receiver, the frequency of a comparison reference clock signal supplied to a fractional-N Phase-Locked Loop (PLL) is dynamically changed such that undesirable reciprocal mixing of reference spurs with known jammers (for example, transmit leakage) is minimized. As the transmit channel changes within a band, and as the transmit leakage frequency changes, a circuit changes the frequency of the comparison reference clock signal such that reference spurs generated by the PLL are moved in frequency so that they do not reciprocally mix with transmitter leakage in undesirable ways. In a second aspect, the PLL is operable either as an integer-N PLL or a fractional-N PLL. In low total receive power situations, the PLL operates as an integer-N PLL to reduce receiver susceptibility to fractional-N spurs. In a third aspect, jammer detect information is used to determine the comparison reference clock signal frequency.

Abstract translation: 在接收机内，提供给分数N锁相环（PLL）的比较参考时钟信号的频率被动态地改变，使得具有已知干扰的参考杂波（例如，传输泄漏）的不期望的相互混合被最小化。 当发射信道在频带内变化时，并且随着发射泄漏频率的变化，电路改变比较参考时钟信号的频率，使得PLL产生的参考杂波频率移动，使得它们不与发射机泄漏相互混合 以不良的方式。 在第二方面，PLL可以作为整数N个PLL或分数N PLL来操作。 在低总接收功率情况下，PLL作为整数N PLL进行操作，以减少接收机对分数N个杂散的敏感性。 在第三方面，使用干扰检测信息来确定比较参考时钟信号频率。