中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

50 records (took 0.019 seconds)

    Method of fabricating semiconductor integrated circuit device
    11.
    发明授权
    Method of fabricating semiconductor integrated circuit device 有权
    制造半导体集成电路器件的方法

    公开(公告)号：US08227308B2

    公开(公告)日：2012-07-24

    申请号：US12647806

    申请日：2009-12-28

    Applicant: Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

    Inventor： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

    IPC: H01L21/8238

    CPC classification number: H01L21/28518 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7843

    Abstract: A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer.

    Abstract translation: 制造半导体集成电路（IC）器件的方法可以包括在衬底上的晶体管的至少一部分上形成第一硅化物层，在第一硅化物层中形成氮以形成第二硅化物层，形成第一应力层 在其上形成有晶体管的衬底上具有拉伸应力，并且用紫外线（UV）光照射第一应力层以形成具有比第一应力层更大的拉伸应力的第二应力层。

    Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors
    13.
    发明申请
    Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors 有权
    具有多层介质膜的晶体管及其制造方法

    公开(公告)号：US20110287622A1

    公开(公告)日：2011-11-24

    申请号：US13195935

    申请日：2011-08-02

    Applicant: Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

    Inventor： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

    IPC: H01L21/28

    CPC classification number: H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

    Abstract: Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

    Abstract translation: 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜，该电介质膜的厚度至少为多层电介质膜的厚度的50％，并且包括金属氧化物，金属硅酸盐，铝酸盐或其混合物，以及上电介质膜 在下介电膜上，上电介质膜包含III族金属氧化物，III族金属氮化物，第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。

    ETCH STOP LAYERS AND METHODS OF FORMING THE SAME
    15.
    发明申请
    ETCH STOP LAYERS AND METHODS OF FORMING THE SAME 有权
    蚀刻停止层及其形成方法

    公开(公告)号：US20110018044A1

    公开(公告)日：2011-01-27

    申请号：US12841245

    申请日：2010-07-22

    Applicant: HA-JIN LIM ,  Pan-Kwi Park ,  Dong-Suk Shin

    Inventor： HA-JIN LIM ,  Pan-Kwi Park ,  Dong-Suk Shin

    IPC: H01L29/78 ,  H01L29/94 ,  H01L27/092 ,  H01L21/31

    CPC classification number: H01L29/76 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/7843

    Abstract: A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress.

    Abstract translation: 半导体器件包括MOSFET和设置在MOSFET上的多个应力层，其中应力层包括设置在MOSFET上的第一应力层和设置在第一应力层上的第二应力层，第一应力层具有第一应力层 应力和第二应力层具有第二应力，并且第一应力不同于第二应力。

    Method of fabricating metal silicate layer using atomic layer deposition technique
    16.
    发明授权
    Method of fabricating metal silicate layer using atomic layer deposition technique 有权
    使用原子层沉积技术制造金属硅酸盐层的方法

    公开(公告)号：US07651729B2

    公开(公告)日：2010-01-26

    申请号：US11127748

    申请日：2005-05-12

    Applicant: Yun-Seok Kim ,  Jong-Pyo Kim ,  Ha-Jin Lim ,  Jae-Eun Park ,  Hyung-Suk Jung ,  Jong-Ho Lee ,  Jong-Ho Yang

    Inventor： Yun-Seok Kim ,  Jong-Pyo Kim ,  Ha-Jin Lim ,  Jae-Eun Park ,  Hyung-Suk Jung ,  Jong-Ho Lee ,  Jong-Ho Yang

    IPC: C23C16/00

    CPC classification number: C23C16/401 ,  C23C16/45529 ,  C23C16/45531

    Abstract: There are provided methods of fabricating a metal silicate layer on a semiconductor substrate using an atomic layer deposition technique. The methods include performing a metal silicate layer formation cycle at least one time in order to form a metal silicate layer having a desired thickness. The metal silicate layer formation cycle includes an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon oxide layer formation cycle Q times. K and Q are integers ranging from 1 to 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, exhausting the metal source gas remaining in a reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor. The silicon oxide layer formation cycle includes supplying a silicon source gas, exhausting the silicon source gas remaining in the reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor.

    Abstract translation: 提供了使用原子层沉积技术在半导体衬底上制造金属硅酸盐层的方法。 所述方法包括至少一次执行金属硅酸盐层形成循环以形成具有所需厚度的金属硅酸盐层。 金属硅酸盐层形成循环包括重复进行金属氧化物层形成循环K次的操作和重复进行氧化硅层形成循环Q次的操作。 K和Q分别为1〜10的整数。 金属氧化物层形成循环包括将金属源气体供给到含有基板的反应器，排出留在反应器内的金属源气体，清洗反应器内部，然后向反应器供给氧化气体的工序。 氧化硅层形成循环包括提供硅源气体，排出留在反应器中的硅源气体以清洁反应器的内部，然后将氧化物气体供应到反应器中。

    Semiconductor devices having different gate dielectric layers and methods of manufacturing the same
    20.
    发明申请
    Semiconductor devices having different gate dielectric layers and methods of manufacturing the same 审中-公开
    具有不同栅介质层的半导体器件及其制造方法

    公开(公告)号：US20070023842A1

    公开(公告)日：2007-02-01

    申请号：US11432717

    申请日：2006-05-12

    Applicant: Hyung-suk Jung ,  Jong-ho Lee ,  Ha-jin Lim ,  Yun-seok Kim

    Inventor： Hyung-suk Jung ,  Jong-ho Lee ,  Ha-jin Lim ,  Yun-seok Kim

    IPC: H01L29/94 ,  H01L29/768 ,  H01L21/8238

    CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3142 ,  H01L21/31645 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: A first transistor includes a first channel region of a first conductivity type located at a first surface region of a semiconductor substrate, a first gate dielectric which includes a first HfO2 layer located over the first channel region, and a first gate located over the first gate dielectric. The first gate includes a first polysilicon layer doped with an impurity of the first conductivity type. The second transistor includes a second channel region of a second conductivity type located at a second surface region of the semiconductor substrate, a second gate dielectric which includes a second HfO2 layer and an Al2O3 layer located over the second channel region, and a second gate located over the second gate dielectric. The second gate includes a second polysilicon layer doped with an impurity of the second conductivity type, and the second conductivity type is opposite the first conductivity type.

    Abstract translation: 第一晶体管包括位于半导体衬底的第一表面区域处的第一导电类型的第一沟道区，包括位于第一沟道区上方的第一HfO 2层的第一栅极电介质，以及 位于第一栅极电介质上方的第一栅极。 第一栅极包括掺杂有第一导电类型的杂质的第一多晶硅层。 第二晶体管包括位于半导体衬底的第二表面区域处的第二导电类型的第二沟道区，包括第二HfO 2层和Al 2 O 2层的第二栅极电介质， 位于第二沟道区上方的第二栅极和位于第二栅极电介质上方的第二栅极。 第二栅极包括掺杂有第二导电类型的杂质的第二多晶硅层，第二导电类型与第一导电类型相反。

Patent Agency Ranking