公开(公告)号：US09673330B2

公开(公告)日：2017-06-06

申请号：US14965982

申请日：2015-12-11

申请人： Jae-yup Chung ,  Yoon-seok Lee ,  Hyun-jo Kim ,  Hwa-sung Rhee ,  Hee-don Jeong ,  Se-wan Park ,  Bo-cheol Jeong

发明人： Jae-yup Chung ,  Yoon-seok Lee ,  Hyun-jo Kim ,  Hwa-sung Rhee ,  Hee-don Jeong ,  Se-wan Park ,  Bo-cheol Jeong

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8238

CPC分类号： H01L21/823481 ,  H01L21/8232 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/785

摘要： An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalk of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalk of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.

公开(公告)号：US20160284706A1

公开(公告)日：2016-09-29

申请号：US15014928

申请日：2016-02-03

申请人： Jae-yup CHUNG ,  Jong-shik YOON ,  Hwa-sung RHEE ,  Hee-don JEONG ,  Je-Min YOO ,  Kyu-man CHA ,  Jong-mil YOUN ,  Hyun-jo KIM

发明人： Jae-yup CHUNG ,  Jong-shik YOON ,  Hwa-sung RHEE ,  Hee-don JEONG ,  Je-Min YOO ,  Kyu-man CHA ,  Jong-mil YOUN ,  Hyun-jo KIM

IPC分类号： H01L27/092 ,  H01L27/02 ,  H01L29/06 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L27/0924 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/7846

摘要： An integrated circuit (IC) device includes a fin-type active region formed in a substrate, a step insulation layer on at least one sidewall of the fin-type active region, and a first high-level isolation layer on the at least one sidewall of the fin-type active region. The fin-type active region protrudes from the substrate and extending in a first direction parallel to a main surface of the substrate, includes a channel region having a first conductivity type, and includes the stepped portion. The step insulation layer contacts the stepped portion of the fin-type active region. The step insulation layer is between the first high-level isolation layer and the at least one sidewall of the fin-type active region. The first high-level isolation layer extends in a second direction that is different from the first direction.

摘要翻译： 集成电路（IC）装置包括形成在衬底中的翅片型有源区，翅片型有源区的至少一个侧壁上的阶梯绝缘层，以及至少一个侧壁上的第一高电平隔​​离层 的鳍式活性区域。 翅片型有源区域从基板突出并且在平行于基板的主表面的第一方向上延伸，包括具有第一导电类型的沟道区域，并且包括台阶部分。 台阶绝缘层接触翅片型有源区的台阶部分。 台阶绝缘层在第一高电平隔​​离层和鳍式有源区的至少一个侧壁之间。 第一高级隔离层在与第一方向不同的第二方向上延伸。

公开(公告)号：US20160163877A1

公开(公告)日：2016-06-09

申请号：US14953769

申请日：2015-11-30

申请人： Jae-Yup Chung ,  Hee-Soo Kang ,  Hee-Don Jeong ,  Se-Wan Park

发明人： Jae-Yup Chung ,  Hee-Soo Kang ,  Hee-Don Jeong ,  Se-Wan Park

IPC分类号： H01L29/786

CPC分类号： H01L29/7848 ,  H01L27/0886 ,  H01L29/785

摘要： A semiconductor device includes a first multi-channel active pattern, a field insulation layer disposed on the first multi-channel active pattern and including a first region and a second region, the first region having a top surface protruding from a top surface of the second region to a top surface of the first multi-channel active pattern, a first gate electrode crossing the first multi-channel active pattern, the first gate electrode being disposed on the field insulation layer, and a first source or drain disposed between the first gate electrode and the first region of the field insulation layer and including a first facet, the first facet being disposed adjacent to the first region of the field insulation layer at a point lower than the top surface of the first multi-channel active pattern.

摘要翻译： 半导体器件包括第一多通道有源图案，设置在第一多通道有源图案上并包括第一区域和第二区域的场绝缘层，第一区域具有从第二多通道有源图案的顶表面突出的顶表面 区域到第一多通道有源图案的顶表面，与第一多通道有源图案交叉的第一栅电极，设置在场绝缘层上的第一栅极电极和设置在第一栅极之间的第一栅极或漏极 电极和场绝缘层的第一区域并且包括第一小面，第一面在比第一多通道活性图案的顶表面低的点处邻近场绝缘层的第一区域设置。

公开(公告)号：US20100112799A1

公开(公告)日：2010-05-06

申请号：US12582983

申请日：2009-10-21

申请人： HEE DON JEONG

发明人： HEE DON JEONG

IPC分类号： H01L21/28

CPC分类号： H01L29/66553 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/7881 ,  H01L29/792

摘要： A method of manufacturing a flash memory device according to an embodiment includes forming a second oxide layer pattern having a mask pattern buried therein on a first nitride layer pattern and a first oxide layer stack on a semiconductor substrate; forming first polysilicon patterns at sidewalls of the buried mask pattern; removing portions of the first oxide layer, the first nitride layer pattern, and the second oxide layer pattern to form a third oxide layer pattern, a second nitride layer pattern, and a fourth oxide layer pattern at lower portions of the first polysilicon patterns and the mask pattern; forming a fifth oxide layer pattern surrounding each of the first polysilicon patterns; forming second polysilicon patterns on sidewalls of the fifth oxide layer pattern; and removing the mask pattern and parts of the third oxide layer pattern and the second nitride layer pattern between the first polysilicon patterns.

摘要翻译： 根据实施例的制造闪速存储器件的方法包括：在第一氮化物层图案和半导体衬底上的第一氧化物层堆叠上形成其掩模图案的第二氧化物层图案; 在掩埋掩模图案的侧壁处形成第一多晶硅图案; 去除第一氧化物层，第一氮化物层图案和第二氧化物层图案的部分以在第一多晶硅图案的下部形成第三氧化物层图案，第二氮化物层图案和第四氧化物层图案，并且 掩模图案 形成围绕所述第一多晶硅图案的每一个的第五氧化物层图案; 在所述第五氧化物层图案的侧壁上形成第二多晶硅图案; 以及在所述第一多晶硅图案之间去除所述掩模图案和所述第三氧化物层图案的部分和所述第二氮化物层图案。