公开(公告)号：US20160247876A1

公开(公告)日：2016-08-25

申请号：US14965982

申请日：2015-12-11

申请人： Jae-yup Chung ,  Yoon-seok LEE ,  Hyun-jo KIM ,  Hwa-sung RHEE ,  Hee-don JEONG ,  Se-wan PARK ,  Bo-cheol JEONG

发明人： Jae-yup Chung ,  Yoon-seok LEE ,  Hyun-jo KIM ,  Hwa-sung RHEE ,  Hee-don JEONG ,  Se-wan PARK ,  Bo-cheol JEONG

IPC分类号： H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823481 ,  H01L21/8232 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/785

摘要： An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalk of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalk of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.

摘要翻译： 集成电路器件包括具有不同导电类型沟道区的第一和第二鳍式有源区，覆盖第一鳍式有源区的人行道的第一器件隔离层和覆盖第二鳍的两侧壁的第二器件隔离层 型活性区。 第一器件隔离层和第二器件隔离层具有不同的堆叠结构。 为了制造集成电路器件，覆盖第一鳍式有源区的两个侧壁的第一器件隔离层和覆盖第二鳍式有源区的人行道的第二器件隔离层在第​​一鳍式有源区 并形成第二鳍型有源区。 第一器件隔离层和第二器件隔离层形成为具有不同的堆叠结构。

公开(公告)号：US08916460B1

公开(公告)日：2014-12-23

申请号：US14270315

申请日：2014-05-05

申请人： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

发明人： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

摘要翻译： 半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。 第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。 第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。 第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。 可以在第二绝缘体的顶表面上形成伪栅电极。 还公开了其制造方法和修改方案。

公开(公告)号：US20100188510A1

公开(公告)日：2010-07-29

申请号：US12531187

申请日：2007-03-13

申请人： Ki-Sung Yoo ,  Chin-Tae Choi ,  Hee-Don Jeong

发明人： Ki-Sung Yoo ,  Chin-Tae Choi ,  Hee-Don Jeong

IPC分类号： H04N5/33 ,  G01B11/14 ,  G01N21/35

CPC分类号： G05D1/0234 ,  G05B2219/37555 ,  G05B2219/40564 ,  G06T7/70 ,  G06T2207/10048 ,  G06T2207/30208

摘要： There are provided a landmark for recognizing a position of a mobile robot moving in an indoor space and an apparatus and method for recognizing the position of the mobile robot by using the landmark. The landmark includes a position recognition part formed of a mark in any position and at least two marks on an X axis and Y axis centered on the mark and further includes an area recognition part formed of a combination of a plurality of marks to distinguish an individual landmark from others. The apparatus may obtain an image of the landmark by an infrared camera, detect the marks forming the landmark, and detect precise position and area information of the mobile robot from the marks.

摘要翻译： 提供了用于识别在室内空间中移动的移动机器人的位置的地标，以及通过使用地标来识别移动机器人的位置的装置和方法。 地标包括由X轴上的任意位置的标记和至少两个标记形成的位置识别部，以标记为中心的Y轴，还包括由多个标记的组合形成的区域识别部，以区分个体 其他地标。 该装置可以通过红外线摄像机获得地标的图像，检测形成地标的标记，并从标记检测移动机器人的精确位置和区域信息。

公开(公告)号：US20150097251A1

公开(公告)日：2015-04-09

申请号：US14569597

申请日：2014-12-12

申请人： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

发明人： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

摘要翻译： 半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。 第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。 第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。 第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。 可以在第二绝缘体的顶表面上形成伪栅电极。 还公开了其制造方法和修改方案。

公开(公告)号：US08076201B2

公开(公告)日：2011-12-13

申请号：US12582983

申请日：2009-10-21

申请人： Hee Don Jeong

发明人： Hee Don Jeong

IPC分类号： H01L21/336

CPC分类号： H01L29/66553 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/7881 ,  H01L29/792

摘要： A method of manufacturing a flash memory device according to an embodiment includes forming a second oxide layer pattern having a mask pattern buried therein on a first nitride layer pattern and a first oxide layer stack on a semiconductor substrate; forming first polysilicon patterns at sidewalls of the buried mask pattern; removing portions of the first oxide layer, the first nitride layer pattern, and the second oxide layer pattern to form a third oxide layer pattern, a second nitride layer pattern, and a fourth oxide layer pattern at lower portions of the first polysilicon patterns and the mask pattern; forming a fifth oxide layer pattern surrounding each of the first polysilicon patterns; forming second polysilicon patterns on sidewalls of the fifth oxide layer pattern; and removing the mask pattern and parts of the third oxide layer pattern and the second nitride layer pattern between the first polysilicon patterns.

摘要翻译： 根据实施例的制造闪速存储器件的方法包括：在第一氮化物层图案和半导体衬底上的第一氧化物层堆叠上形成其掩模图案的第二氧化物层图案; 在掩埋掩模图案的侧壁处形成第一多晶硅图案; 去除第一氧化物层，第一氮化物层图案和第二氧化物层图案的部分以在第一多晶硅图案的下部形成第三氧化物层图案，第二氮化物层图案和第四氧化物层图案，并且 掩模图案 形成围绕所述第一多晶硅图案的每一个的第五氧化物层图案; 在所述第五氧化物层图案的侧壁上形成第二多晶硅图案; 以及在所述第一多晶硅图案之间去除所述掩模图案和所述第三氧化物层图案的部分和所述第二氮化物层图案。

公开(公告)号：US20090315100A1

公开(公告)日：2009-12-24

申请号：US12478328

申请日：2009-06-04

申请人： Hee-Don Jeong

发明人： Hee-Don Jeong

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  Y10S438/954

摘要： Disclosed is a method of manufacturing a semiconductor device. The method includes forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate, and forming a recess over the semiconductor substrate by etching the ONO layer, forming a vertical structure pattern being higher than the ONO layer over the recess, sequentially forming a spacer oxide film and a first gate poly over the side wall of the vertical structure pattern, and forming a nitride film spacer at a partial region of the side wall of the first gate poly, removing the nitride film spacer, and forming a second gate poly in a spacer shape over the side wall of the first gate poly, and forming a first split gate and a second split gate, symmetrically divided from each other, by removing the vertical structure pattern.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括在半导体衬底上形成氧化物 - 氧化物（ONO）层，并通过蚀刻ONO层在半导体衬底上形成凹陷，在凹槽上形成高于ONO层的垂直结构图案，依次形成 间隔氧化物膜和在垂直结构图案的侧壁上的第一栅极聚合物，并且在第一栅极聚合物的侧壁的部分区域处形成氮化物膜间隔物，去除氮化物膜间隔物，并形成第二栅极 在第一栅极多晶硅的侧壁上形成间隔物形状的多晶硅，并且通过去除垂直结构图案形成对称分割的第一分离栅极和第二分离栅极。

公开(公告)号：US09922979B2

公开(公告)日：2018-03-20

申请号：US15014928

申请日：2016-02-03

申请人： Jae-yup Chung ,  Jong-shik Yoon ,  Hwa-sung Rhee ,  Hee-don Jeong ,  Je-Min Yoo ,  Kyu-man Cha ,  Jong-mil Youn ,  Hyun-jo Kim

发明人： Jae-yup Chung ,  Jong-shik Yoon ,  Hwa-sung Rhee ,  Hee-don Jeong ,  Je-Min Yoo ,  Kyu-man Cha ,  Jong-mil Youn ,  Hyun-jo Kim

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L27/088 ,  H01L27/02 ,  H01L21/762 ,  H01L21/8238

CPC分类号： H01L27/0924 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/7846

摘要： An integrated circuit (IC) device includes a fin-type active region formed in a substrate, a step insulation layer on at least one sidewall of the fin-type active region, and a first high-level isolation layer on the at least one sidewall of the fin-type active region. The fin-type active region protrudes from the substrate and extending in a first direction parallel to a main surface of the substrate, includes a channel region having a first conductivity type, and includes the stepped portion. The step insulation layer contacts the stepped portion of the fin-type active region. The step insulation layer is between the first high-level isolation layer and the at least one sidewall of the fin-type active region. The first high-level isolation layer extends in a second direction that is different from the first direction.

公开(公告)号：US09190407B2

公开(公告)日：2015-11-17

申请号：US14569597

申请日：2014-12-12

申请人： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

发明人： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/49

CPC分类号： H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

摘要翻译： 半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。 第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。 第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。 第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。 可以在第二绝缘体的顶表面上形成伪栅电极。 还公开了其制造方法和修改方案。

公开(公告)号：US07943495B2

公开(公告)日：2011-05-17

申请号：US12478328

申请日：2009-06-04

申请人： Hee-Don Jeong

发明人： Hee-Don Jeong

IPC分类号： H01L21/26 ,  H01L21/42

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  Y10S438/954

摘要： Disclosed is a method of manufacturing a semiconductor device. The method includes forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate, and forming a recess over the semiconductor substrate by etching the ONO layer, forming a vertical structure pattern being higher than the ONO layer over the recess, sequentially forming a spacer oxide film and a first gate poly over the side wall of the vertical structure pattern, and forming a nitride film spacer at a partial region of the side wall of the first gate poly, removing the nitride film spacer, and forming a second gate poly in a spacer shape over the side wall of the first gate poly, and forming a first split gate and a second split gate, symmetrically divided from each other, by removing the vertical structure pattern.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括在半导体衬底上形成氧化物 - 氧化物（ONO）层，并通过蚀刻ONO层在半导体衬底上形成凹陷，在凹槽上形成高于ONO层的垂直结构图案，依次形成 间隔氧化物膜和在垂直结构图案的侧壁上的第一栅极聚合物，并且在第一栅极聚合物的侧壁的部分区域处形成氮化物膜间隔物，去除氮化物膜间隔物，并形成第二栅极 在第一栅极多晶硅的侧壁上形成间隔物形状的多晶硅，并且通过去除垂直结构图案形成对称分割的第一分离栅极和第二分离栅极。

公开(公告)号：US08368759B2

公开(公告)日：2013-02-05

申请号：US12531187

申请日：2007-03-13

申请人： Ki-Sung Yoo ,  Chin-Tae Choi ,  Hee-Don Jeong

发明人： Ki-Sung Yoo ,  Chin-Tae Choi ,  Hee-Don Jeong

IPC分类号： G06F19/00

CPC分类号： G05D1/0234 ,  G05B2219/37555 ,  G05B2219/40564 ,  G06T7/70 ,  G06T2207/10048 ,  G06T2207/30208

摘要： There are provided a landmark for recognizing a position of a mobile robot moving in an indoor space and an apparatus and method for recognizing the position of the mobile robot by using the landmark. The landmark includes a position recognition part formed of a mark in any position and at least two marks on an X axis and Y axis centered on the mark and further includes an area recognition part formed of a combination of a plurality of marks to distinguish an individual landmark from others. The apparatus may obtain an image of the landmark by an infrared camera, detect the marks forming the landmark, and detect precise position and area information of the mobile robot from the marks.

摘要翻译： 提供了用于识别在室内空间中移动的移动机器人的位置的地标，以及通过使用地标来识别移动机器人的位置的装置和方法。 地标包括由X轴上的任意位置的标记和至少两个标记形成的位置识别部，以标记为中心的Y轴，还包括由多个标记的组合形成的区域识别部，以区分个体 其他地标。 该装置可以通过红外线摄像机获得地标的图像，检测形成地标的标记，并从标记检测移动机器人的精确位置和区域信息。