公开(公告)号：US07649292B2

公开(公告)日：2010-01-19

申请号：US11583073

申请日：2006-10-19

申请人： Kazunari Moriya ,  Yukio Inaguma ,  Hiroo Fuma

发明人： Kazunari Moriya ,  Yukio Inaguma ,  Hiroo Fuma

IPC分类号： H02K16/00

CPC分类号： H02K16/02 ,  B60K6/26 ,  B60K6/445 ,  B60K6/448 ,  B60K6/48 ,  B60K2006/262 ,  B60L7/14 ,  B60L11/123 ,  B60L11/14 ,  B60L15/20 ,  B60L15/2009 ,  B60L2210/40 ,  B60L2220/12 ,  B60L2220/14 ,  B60L2220/52 ,  B60L2240/423 ,  H02K7/006 ,  H02K16/00 ,  H02P2207/03 ,  Y02T10/6217 ,  Y02T10/6221 ,  Y02T10/6239 ,  Y02T10/6243 ,  Y02T10/641 ,  Y02T10/644 ,  Y02T10/645 ,  Y02T10/7077 ,  Y02T10/7241 ,  Y02T10/7275

摘要： An induction machine includes a stator provided with stator windings and a first rotor provided with first rotor windings, and generates an induction current in one of the stator windings and the first rotor windings by a rotating magnetic field generated in the other of the stator windings and the first rotor windings. A synchronous machine includes a second rotor which is provided with second rotor windings connected to the first rotor windings and coupled to the first rotor, and a third rotor which is provided with permanent magnets and rotatable independent of the second rotor, and a torque acts between the second rotor and the third rotor due to the interaction between the rotating magnetic field generated in the second rotor windings and the field flux generated in the permanent magnets.

摘要翻译： 感应电动机包括定子绕组的定子和设置有第一转子绕组的第一转子，并且通过在另一个定子绕组中产生的旋转磁场在定子绕组和第一转子绕组中的一个中产生感应电流， 第一转子绕组。 同步电机包括第二转子，其具有连接到第一转子绕组并且耦合到第一转子的第二转子绕组，以及设置有永磁体并且独立于第二转子旋转的第三转子，并且扭矩作用在 第二转子和第三转子由于在第二转子绕组中产生的旋转磁场与在永磁体中产生的磁场通量之间的相互作用而产生。

公开(公告)号：US06956341B2

公开(公告)日：2005-10-18

申请号：US10627774

申请日：2003-07-28

申请人： Hideo Nakai ,  Hiroo Fuma ,  Yukio Inaguma ,  Seiji Nakamura

发明人： Hideo Nakai ,  Hiroo Fuma ,  Yukio Inaguma ,  Seiji Nakamura

IPC分类号： H02P29/00 ,  H02P21/00 ,  H02P25/22 ,  H02P3/08

CPC分类号： H02P25/22 ,  H02P21/22

摘要： Two inverters (INV1, INV2) supply phase currents to three-phase coils (Y1, Y2). Although two phase currents must conventionally be measured and four current sensors are thus required, according to the present invention, the number of phase currents to be measured is reduced as a result of use of an observer for phase current estimation.

摘要翻译： 两个反相器（INV 1，INV 2）向三相线圈（Y 1，Y 2）提供相电流。 虽然传统上需要测量两相电流，因此需要四个电流传感器，但根据本发明，由于使用观测器进行相电流估计，所以要测量的相电流的数量减少。

公开(公告)号：US6020600A

公开(公告)日：2000-02-01

申请号：US938805

申请日：1997-09-26

申请人： Takeshi Miyajima ,  Norihito Tokura ,  Kazukuni Hara ,  Hiroo Fuma

发明人： Takeshi Miyajima ,  Norihito Tokura ,  Kazukuni Hara ,  Hiroo Fuma

IPC分类号： H01L21/04 ,  H01L29/08 ,  H01L29/24 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/66068 ,  H01L29/7828 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/4236 ,  Y10S438/981

摘要： A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n.sup.+ type silicon carbide semiconductor substrate 1, an n.sup.- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n.sup.+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n.sup.+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n.sup.- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n.sup.+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n.sup.- type silicon carbide semiconductor layer 2 in the side face of the trench 9. A gate electrode layer 13 is disposed through a gate insulating layer 12 within the trench 9. A source electrode layer 15 is provided on the surface of the p type silicon carbide semiconductor layer 3 and on the surface of the n.sup.+ type source region 6, and a drain electrode layer 16 is provided on the surface of the n.sup.+ type silicon carbide semiconductor substrate 1.

摘要翻译： 提供了具有高阻断电压，低损耗和低阈值电压的碳化硅半导体器件。 n +型碳化硅半导体衬底1，n型碳化硅半导体衬底2和p型碳化硅半导体层3相互层叠在一起。 在p型碳化硅半导体层3的表面的预定区域中形成n +型源极区6，并且形成沟槽9，以延伸穿过n +型源极区6和p型碳化硅半导体层 在n型碳化硅半导体层2的表面上延伸设置有薄膜半导体层（n型或p型）11a，在n +型源极区6，p型碳化硅半导体层3的表面上， 在沟槽9的侧面中的n型碳化硅半导体层2.栅极电极层13通过沟槽9内的栅极绝缘层12设置。源电极层15设置在p型表面上 碳化硅半导体层3和n +型源极区6的表面，以及在n +型碳化硅半导体衬底1的表面上设置漏电极层16。

公开(公告)号：US5915180A

公开(公告)日：1999-06-22

申请号：US418147

申请日：1995-04-05

申请人： Kazukuni Hara ,  Norihito Tokura ,  Takeshi Miyajima ,  Hiroo Fuma ,  Hiroyuki Kano

发明人： Kazukuni Hara ,  Norihito Tokura ,  Takeshi Miyajima ,  Hiroo Fuma ,  Hiroyuki Kano

IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L21/335

CPC分类号： H01L29/7813 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  Y10S438/931

摘要： A semiconductor device, which has an oxide laver with the thickness thereof being varied from portion to portion of the inner surface of a trench and can be easily produced, and a process of producing the same. An n.sup.+ type single crystal SiC substrate is formed of SiC of hexagonal system having a carbon face with a (0001) face orientation as a surface, and an n type epitaxial layer and a p type epitaxial layer are successively laminated onto the substrate. An n.sup.+ source region is provided within the p type epitaxial layer, and the trench extends through the source region and the epitaxial layer into the semiconductor substrate. The side face of the trench is almost perpendicular to the surface of the epitaxial layer with the bottom face of the trench having a plane parallel to the surface of the epitaxial layer. The thickness of a gate oxide layer, formed by thermal oxidation, on the bottom face of the trench is larger than the thickness of the gate oxide layer on the side face of the trench. A gate electrode layer is provided on the surface of the oxide layer, formed by thermal oxidation, within the trench, a source electrode layer is provided on the epitaxial layer and the source region, and a drain electrode layer is provided on the back surface of the semiconductor substrate.

摘要翻译： 具有其厚度的氧化物紫菜的半导体器件可以从沟槽的内表面的一部分变化，并且可以容易地制造，以及其制造方法。 n +型单晶SiC衬底由具有（0001）面取向的碳面作为表面的六方晶系的SiC形成，并且n型外延层和p型外延层依次层叠在衬底上。 在p型外延层内提供n +源极区，并且沟槽延伸穿过源区和外延层进入半导体衬底。 沟槽的侧面几乎垂直于外延层的表面，沟槽的底面具有平行于外延层的表面的平面。 在沟槽的底面上通过热氧化形成的栅极氧化物层的厚度大于沟槽侧面上的栅极氧化物层的厚度。 在氧化层形成的氧化层的表面上，在沟槽内设置栅极电极层，在外延层和源极区域设置有源电极层，在其背面设有漏电极层 半导体衬底。