公开(公告)号：US06856265B2

公开(公告)日：2005-02-15

申请号：US10604527

申请日：2003-07-29

Applicant: Tai-Haur Kuo ,  Kuo-Hsin Chen ,  Jyh-Fong Lin ,  Hsin-Chieh Lin

Inventor： Tai-Haur Kuo ,  Kuo-Hsin Chen ,  Jyh-Fong Lin ,  Hsin-Chieh Lin

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/34 ,  H03M1/36 ,  H03M3/00

CPC classification number: H03M1/1023 ,  H03M1/0682 ,  H03M1/1004 ,  H03M1/206 ,  H03M1/365

Abstract: An analog-to-digital data converter converts an input signal to corresponding digital signals. The data converter includes two sets of comparison units arranged in an interlaced sense to alternatively analyze the input signal, generate digital signals corresponding to the result of comparing the input signal and reference signals. Each of the comparison units has a positive output and a negative output, and the digital signal is generated by the negative output and the positive output of the comparison units in a differential way. When the comparison units of one set are performing auto-zeroing, the comparison units of the other set perform the data conversion to generate corresponding digital signals.

Abstract translation: 模拟数字数据转换器将输入信号转换成相应的数字信号。 数据转换器包括以隔行方式布置的两组比较单元，以交替地分析输入信号，产生对应于比较输入信号和参考信号的结果的数字信号。 每个比较单元具有正输出和负输出，并且数字信号以差分方式由负输出和比较单元的正输出产生。 当一组的比较单元正在执行自动归零时，另一组的比较单元执行数据转换以产生相应的数字信号。

公开(公告)号：US06687320B1

公开(公告)日：2004-02-03

申请号：US09322072

申请日：1999-05-27

Applicant: You-Ming Chiu ,  Jiin Lai ,  Jyhfong Lin ,  Hsin-Chieh Lin ,  Wei-Yu Wang

Inventor： You-Ming Chiu ,  Jiin Lai ,  Jyhfong Lin ,  Hsin-Chieh Lin ,  Wei-Yu Wang

IPC: H03D324

CPC classification number: H03L7/081 ,  G06F1/08 ,  G06F1/10 ,  H03L7/18

Abstract: A phase lock loop (PLL) clock generator with programmable frequency and skew is provided in the present invention, in which frequency of clock signals generated can be dynamically changed and skew of the clock signals generated can be dynamically adjusted by a computer program. Also, the signal skew due to the change of loading can be compensated. Therefore, the PLL clock generator based on a closed-loop configuration can better control the skew of clock signals to provide higher stability and durability to the system.

Abstract translation: 在本发明中提供了具有可编程频率和偏斜的锁相环（PLL）时钟发生器，其中产生的时钟信号的频率可以被动态地改变，并且可以通过计算机程序动态地调整产生的时钟信号的偏移。 此外，可以补偿由于负载变化引起的信号偏移。 因此，基于闭环配置的PLL时钟发​​生器可以更好地控制时钟信号的偏斜，为系统提供更高的稳定性和耐久性。

公开(公告)号：US06642866B2

公开(公告)日：2003-11-04

申请号：US10063204

申请日：2002-03-28

Applicant: Tai-Haur Kuo ,  Kuo-Hsin Chen ,  Jyh-Fong Lin ,  Hsin-Chieh Lin

Inventor： Tai-Haur Kuo ,  Kuo-Hsin Chen ,  Jyh-Fong Lin ,  Hsin-Chieh Lin

IPC: H03M106

CPC classification number: H03M1/1004 ,  H03M1/0682 ,  H03M1/1023 ,  H03M1/365

Abstract: An analog-to-digital data converter converts an input signal to corresponding digital signals. The data converter includes two sets of comparison units arranged in an interlaced sense to alternatively analyze the input signal, generate digital signals corresponding to the result of comparing the input signal and reference signals. Each of the comparison units has a positive output and a negative output, and the digital signal is generated by the negative output and the positive output of the comparison units in a differential way. When the comparison units of one set are performing auto-zeroing, the comparison units of the other set perform the data conversion to generate corresponding digital signals.

Abstract translation: 模拟数字数据转换器将输入信号转换成相应的数字信号。 数据转换器包括以隔行方式布置的两组比较单元，以交替地分析输入信号，产生对应于比较输入信号和参考信号的结果的数字信号。 每个比较单元具有正输出和负输出，并且数字信号以差分方式由负输出和比较单元的正输出产生。 当一组的比较单元正在执行自动归零时，另一组的比较单元执行数据转换以产生相应的数字信号。

公开(公告)号：US06400197B2

公开(公告)日：2002-06-04

申请号：US09766952

申请日：2001-01-22

Applicant: Jiin Lai ,  Hsin-Chieh Lin ,  Kuo-Ping Liu

Inventor： Jiin Lai ,  Hsin-Chieh Lin ,  Kuo-Ping Liu

IPC: H03L700

CPC classification number: G06F5/06 ,  G06F1/10 ,  G06F2205/104 ,  H03L7/0814

Abstract: A signal delay device having an internal delay lock loop for calibrating the delay interval. The signal delay device receives an input signal and then outputs the signal after a pre-defined delay period. The input signal varies according to a reference clock signal, and the required delay period is a quarter cycle of the clock signal. The delay device includes a multiplexer, an inverter, a phase detector, a counter and a delay element. During calibration, the phase detector, the counter and the delay element form a delay lock loop that can set up the delay time automatically.

Abstract translation: 一种具有用于校准延迟间隔的内部延迟锁定环路的信号延迟装置。 信号延迟装置接收输入信号，然后在预定义的延迟周期之后输出信号。 输入信号根据参考时钟信号而变化，所需的延迟周期是时钟信号的四分之一周期。 延迟装置包括多路复用器，反相器，相位检测器，计数器和延迟元件。 在校准期间，相位检测器，计数器和延迟元件形成可以自动设置延迟时间的延迟锁定环。

公开(公告)号：US06292521B1

公开(公告)日：2001-09-18

申请号：US09150365

申请日：1998-09-09

Applicant: Jiin Lai ,  Hsin-Chieh Lin ,  Fang-Yi Chen

Inventor： Jiin Lai ,  Hsin-Chieh Lin ,  Fang-Yi Chen

IPC: H04L700

CPC classification number: H04L7/0338 ,  H03L7/0805 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0033

Abstract: A phase lock device and method applicable to a data transmission system, particularly to a high speed transmission system are provided. Based on that the optimum operation margin for delaying data strobe is to shift the edge of data strobe to the middle region of data signal, the phase lock device and method suggest a solution, by analyzing the influence of environmental and operational conditions on delaying data strobe and system clock, to adapt delay element to the variation of environmental and operational conditions, so that the delay of data strobe is always in such a range that the data receiver can be enabled to do accurate and reliable data reading, regardless of external interference.

Abstract translation: 提供一种适用于数据传输系统，特别是高速传输系统的锁相装置和方法。 基于数据选通延迟的最佳运行余量是将数据选通的边沿移动到数据信号的中间区域，相位锁定装置和方法通过分析环境和运行条件对延迟数据选通的影响来提出解决方案 和系统时钟，以使延迟元件适应环境和操作条件的变化，使得数据选通的延迟总是处于使数据接收器能够进行精确和可靠的数据读取的范围，而不管外部干扰如何。