Touch panel
    11.
    发明授权
    Touch panel 有权
    触控面板

    公开(公告)号:US08809717B2

    公开(公告)日:2014-08-19

    申请号:US13570141

    申请日:2012-08-08

    CPC classification number: G06F3/044

    Abstract: A touch panel is provided that includes: a substrate; a plurality of X-axis lines disposed on the substrate; a plurality of Y-axis lines crossing the plurality of X-axis lines; and an insulating layer interposed between the X-axis lines and the Y-axis lines, in which at least one first X-axis line and at least one second X-axis line selected from among the plurality of X-axis lines are connected by a first connection portion, and among the plurality of Y-axis lines, a Y-axis line crossing the first X-axis line and the second X-axis line has a first area in a region where the Y-axis line overlaps the first X-axis line and a second area in a region where the Y-axis line overlaps the second X-axis line, and the first area and the second area are different from each other.

    Abstract translation: 提供一种触摸面板,其包括:基板; 设置在所述基板上的多个X轴线; 与所述多个X轴线交叉的多个Y轴线; 以及介于X轴线和Y轴线之间的绝缘层,其中从多个X轴线中选择的至少一个第一X轴线和至少一个第二X轴线通过 第一连接部,并且在所述多个Y轴线之中,与所述第一X轴线和所述第二X轴线交叉的Y轴线具有在所述Y轴线与所述第一连接部的所述第一 X轴线和Y轴线与第二X轴线重叠的区域中的第二区域,第一区域和第二区域彼此不同。

    PROTRUDING POST RESISTIVE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    13.
    发明申请
    PROTRUDING POST RESISTIVE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    推进后电阻记忆体装置及其制造方法

    公开(公告)号:US20130140516A1

    公开(公告)日:2013-06-06

    申请号:US13599259

    申请日:2012-08-30

    Abstract: A resistive memory device may include a substrate, gate electrode structures, a first impurity region, a second impurity region, a first metal silicide pattern and a second metal silicide pattern. The substrate may have a first region where isolation patterns and first active patterns may be alternately arranged in a first direction, and a second region where linear second active patterns may be extended in the first direction. The gate electrode structures may be arranged between the first region and the second region of the substrate. The first and second impurity regions may be formed in the first and second impurity regions. The first metal silicide pattern may have an isolated shape configured to make contact with an upper surface of the first impurity region. The second metal silicide pattern may make contact with an upper surface of the second impurity region.

    Abstract translation: 电阻式存储器件可以包括衬底,栅电极结构,第一杂质区,第二杂质区,第一金属硅化物图案和第二金属硅化物图案。 衬底可以具有其中隔离图案和第一有源图案可以沿第一方向交替布置的第一区域,以及可以在第一方向上延伸线性第二有源图案的第二区域。 栅极电极结构可以布置在衬底的第一区域和第二区域之间。 第一和第二杂质区可以形成在第一和第二杂质区中。 第一金属硅化物图案可以具有被配置为与第一杂质区域的上表面接触的隔离形状。 第二金属硅化物图案可以与第二杂质区域的上表面接触。

    Vacuum cleaner
    14.
    发明授权
    Vacuum cleaner 有权
    吸尘器

    公开(公告)号:US07854782B2

    公开(公告)日:2010-12-21

    申请号:US11975434

    申请日:2007-10-19

    CPC classification number: A47L9/108 A47L5/28 A47L9/1683 Y10S55/03

    Abstract: A vacuum cleaner includes a vacuum cleaner body, a cyclone unit which is mounted at the vacuum cleaner body, and separates dust from drawn air, a dust separating unit which is engaged with a lower end of the cyclone unit, said dust separating unit being configured to collect separated dust, said dust separating unit being detachable from the cyclone, and said dust separating unit comprising a compressing plate compressing the collected dust; and a driving unit which is disposed at a lower end of the dust separating unit, said driving unit being configured to ascend and descend the dust separating unit to be detachably connected to the cyclone unit and drives the compressing plate.

    Abstract translation: 真空吸尘器包括真空吸尘器主体,安装在真空吸尘器本体上的旋风单元,并将灰尘与抽吸空气分离;灰尘分离单元,其与旋风单元的下端接合,所述分离单元配置 收集分离的灰尘,所述灰尘分离单元可与旋风分离器分离,所述灰尘分离单元包括压缩收集的灰尘的压缩板; 以及驱动单元,其布置在所述除尘单元的下端,所述驱动单元被配置为使所述灰尘分离单元上升和下降以可拆卸地连接到所述旋风单元并驱动所述压缩板。

    Delay locked loop
    18.
    发明授权
    Delay locked loop 有权
    延迟锁定环路

    公开(公告)号:US07554371B2

    公开(公告)日:2009-06-30

    申请号:US11412803

    申请日:2006-04-28

    CPC classification number: H03L7/0814 H03L7/089

    Abstract: A delay locked loop for generating an internal clock signal locked to an external clock signal includes: a phase detector for detecting a phase difference between the external clock signal and the internal clock signal; a delay unit controller for generating a control signal and a selection signal in response to an output signal of the phase detector; a variable delay device (VDD), responsive to the control signal and a selection signal, to produce a delayed version of the external clock signal on a VDD output line, the variable delay device being configured such that, if the external clock signal undergoes a change from a first frequency to a second frequency significantly different than the first frequency, then a resultant load on the VDD output line nonetheless remains substantially the same.

    Abstract translation: 用于产生锁定到外部时钟信号的内部时钟信号的延迟锁定环路包括:用于检测外部时钟信号和内部时钟信号之间的相位差的相位检测器; 延迟单元控制器,用于响应于相位检测器的输出信号产生控制信号和选择信号; 可变延迟装置(VDD),响应于控制信号和选择信号,在VDD输出线上产生外部时钟信号的延迟版本,该可变延迟装置被配置为使得如果外部时钟信号经历 从第一频率改变到与第一频率显着不同的第二频率,则VDD输出线上的合成负载仍然保持基本相同。

Patent Agency Ranking