公开(公告)号：US20240136297A1

公开(公告)日：2024-04-25

申请号：US18112590

申请日：2023-02-22

Applicant: Institute of Semiconductors, Guangdong Academy of Sciences

Inventor： Yingqiang YAN ,  Chuan HU ,  Yao WANG ,  Wei ZHENG ,  Zhitao CHEN

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L2224/24137 ,  H01L2224/24141 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/95001 ,  H01L2224/96

Abstract: A multi-chip interconnection package structure with a heat dissipation plate and a preparation method thereof are provided. The multi-chip interconnection package structure with a heat dissipation plate includes a fine circuit layer, at least one die, a heat dissipation plate, a plastic package body, and a package circuit layer, the heat dissipation plate is provided on the fine circuit layer, and is mounted on a side of the die away from the fine circuit layer, the plastic package body wraps the die and the heat dissipation plate, and the package circuit layer is provided on the plastic package body.

公开(公告)号：US11869872B2

公开(公告)日：2024-01-09

申请号：US17634081

申请日：2021-08-05

Applicant: Institute of Semiconductors, Guangdong Academy of Sciences

Inventor： Yao Wang ,  Yunzhi Ling ,  Yinhua Cui ,  Chuan Hu ,  Zibai Li ,  Wei Zhao ,  Zhitao Chen

IPC: H01L23/02 ,  H01L25/065 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08113 ,  H01L2224/08146 ,  H01L2224/80896 ,  H01L2924/15153

Abstract: A chip stack packaging structure and method includes: a base chip layer, including a base chip with pins on the front surface; at least one stacked chip layer, which is formed on the base chip layer, has an inter-chip insulating layer and at least one stacked chip attached to the insulating layer and pins on the front surface, where the front surface of the stacked chip faces the front surface of the base chip; and a top insulating layer, stacked on the stacked chip layer farthest from the base chip layer. A vertical interconnection hole is formed inside the inter-chip insulating layer to allow the corresponding pins to be communicated vertically so as to be electrically connected. Inside the vertical interconnection hole, a conductive material layer is formed that makes the corresponding pins electrically connected; the stacked chip is thinned and reduced after being attached to the inter-chip insulating layer.

公开(公告)号：US20230402525A1

公开(公告)日：2023-12-14

申请号：US18035663

申请日：2021-12-27

Applicant: Institute of Semiconductors, Guangdong Academy of Sciences

Inventor： Chengguo LI ,  Qiaoyu ZENG ,  Xuebing YIN ,  Xiaoming GE ,  Zhitao CHEN

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/06 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/0603 ,  H01L29/7786

Abstract: Embodiments of the present application relate to the technical field of semiconductors, and provide a manufacturing method for an N-polar GaN transistor structure and a semiconductor structure. A Ga-polar epitaxial functional layer is formed by depositing, a supporting substrate is formed on the epitaxial functional layer by bonding, after the epitaxial structure is inverted, a structural substrate and a buffer layer are removed, and a source, a drain, and a gate are manufactured on the side of the exposed epitaxial functional layer away from the supporting substrate, to form an N-polar GaN transistor structure.

公开(公告)号：US11609672B1

公开(公告)日：2023-03-21

申请号：US17654524

申请日：2022-03-11

Applicant: Institute of Semiconductors, Guangdong Academy of Sciences

Inventor： Zibai Li ,  Yao Wang ,  Chuan Hu ,  Boqian Chen ,  Zhitao Chen

IPC: G06F3/044 ,  G06F3/041

Abstract: A touch control substrate, a preparation method thereof, a touch control module, and a display device are provided. The touch control substrate comprises: a substrate, a conductive functional layer, and a second protection medium. The conductive functional layer is arranged on one side of the substrate, and comprises patterned nano conductive structure, first protection medium, and frame lead structure. The conductive functional layer is protected by providing a two-layer protection medium structure, wherein the first protection medium fixes the structural position of the nano conductive layer and protects the partial structure of the conductive functional layer, and the second protection medium at least completely covers the nano conductive layer located in the conductive functional area; and at the same time, the touch control substrate directly disposes the frame lead layer in the peripheral area of the nano conductive layer, making the frame lead directly contacting the nano conductive layer.

公开(公告)号：US20220254651A1

公开(公告)日：2022-08-11

申请号：US17434480

申请日：2021-02-08

Applicant: Institute of Semiconductors, Guangdong Academy of Sciences

Inventor： Yao WANG ,  Zibai LI ,  Yunzhi LING ,  Xun XIANG ,  Yinhua CUI ,  Chuan HU ,  Zhitao CHEN

IPC: H01L21/48 ,  H01L23/538 ,  H01L25/065

Abstract: Provided are a chip interconnection package structure and method, including: forming a sacrificial pattern layer on a support structure; forming an interconnection winding pattern layer on the sacrificial pattern layer, wherein the interconnection winding pattern layer is corresponding to a sacrificial pattern of the sacrificial pattern layer in position; forming a first insulating layer on the interconnection winding pattern layer; forming a plurality of chips arranged at intervals on the first insulating layer, wherein the plurality of chips are respectively corresponding to the interconnection winding pattern of the interconnection winding pattern layer in position; and removing the support structure, and forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, and making the first interconnection hole aligned and communicated with a first interconnection pin of the chip corresponding in projection position.

公开(公告)号：US20240007072A1

公开(公告)日：2024-01-04

申请号：US18038371

申请日：2021-07-27

Applicant: INSTITUTE OF SEMICONDUCTORS, GUANGDONG ACADEMY OF SCIENCES

Inventor： Yingqiang YAN ,  Chuan HU ,  Xun XIANG ,  Wei ZHENG ,  Zhitao CHEN ,  Zhikuan CHEN

IPC: H03H1/00

CPC classification number: H03H1/0007 ,  H03H2001/0021

Abstract: A filter radio frequency module packaging structure and a method for manufacturing same is disclosed. A first filter chip of the filter radio frequency module packaging structure comprises a chip main body and a wall structure. The wall structure, the functional surface, and a substrate together define a closed cavity, or the wall structure and the functional surface together define a closed cavity. An encapsulation material wraps the first filter chip.

公开(公告)号：US20230178514A1

公开(公告)日：2023-06-08

申请号：US17634081

申请日：2021-08-05

Applicant: Institute of Semiconductors, Guangdong Academy of Sciences

Inventor： Yao Wang ,  Yunzhi Ling ,  Yinhua Cui ,  Chuan Hu ,  Zibai Li ,  Wei Zhao ,  Zhitao Chen

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L25/0652 ,  H01L23/49827 ,  H01L24/08 ,  H01L25/50 ,  H01L24/80 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L2224/80896 ,  H01L2224/08113 ,  H01L2224/08146 ,  H01L2924/15153

Abstract: A chip stack packaging structure and method includes: a base chip layer, including a base chip with pins on the front surface; at least one stacked chip layer, which is formed on the base chip layer, has an inter-chip insulating layer and at least one stacked chip attached to the insulating layer and pins on the front surface, where the front surface of the stacked chip faces the front surface of the base chip; and a top insulating layer, stacked on the stacked chip layer farthest from the base chip layer. A vertical interconnection hole is formed inside the inter-chip insulating layer to allow the corresponding pins to be communicated vertically so as to be electrically connected. Inside the vertical interconnection hole, a conductive material layer is formed that makes the corresponding pins electrically connected; the stacked chip is thinned and reduced after being attached to the inter-chip insulating layer.

公开(公告)号：US20220375892A1

公开(公告)日：2022-11-24

申请号：US17438528

申请日：2021-05-21

Applicant: Institute of Semiconductors, Guangdong Academy of Sciences

Inventor： Yinhua CUI ,  Yao WANG ,  Yunzhi LING ,  Wei ZHAO ,  Zhitao CHEN ,  Chuan HU

IPC: H01L23/00 ,  H01L23/10

Abstract: A chip packaging method and a chip packaging structure is disclosed. The method includes: attaching at least two chips to one side of substrate by adhesive layer, wherein device surface of the chip faces the substrate, and the substrate is provided therein with substrate wiring structure and/or chip; performing thinning treatment on the at least two chips provided on one side of the substrate, wherein the thinning treatment includes etching only the chips to reduce the thickness of the chips; plastically sealing the chips having undergone the thinning treatment to form a plastically sealed arrangement layer, and stacking at least two such plastically sealed arrangement layers on the substrate along plastic sealing direction; and punching the chips having undergone the thinning treatment to form first interconnection hole connecting the chips having undergone the thinning treatment to the substrate wiring structure, the chip in substrate, or the plastically sealed arrangement layer.