公开(公告)号：US3630043A

公开(公告)日：1971-12-28

申请号：US3630043D

申请日：1970-05-18

Applicant: JAN MULDER

Inventor： MULDER JAN

IPC: A61B18/02 ,  F17C3/08 ,  F25B9/00 ,  F25D9/00 ,  F25D16/00 ,  F25D17/02 ,  F25D31/00

CPC classification number: A61B18/02 ,  F17C3/085 ,  F17C2205/0323 ,  F17C2221/012 ,  F17C2227/03 ,  F17C2227/0337 ,  F25B9/00 ,  F25D9/00 ,  F25D16/00 ,  F25D17/02 ,  F25D31/00 ,  Y02E60/321 ,  Y02P90/45

Abstract: An apparatus and method of transporting cold from a source of cold to an object to be cooled, with a quantity of cold stored in a regenerator, which cold can subsequently be used during cooling the object in addition to the cold from the cold source, thereby temporarily providing a greater cooling capacity than can be supplied by the cold source alone.

公开(公告)号：US08410820B2

公开(公告)日：2013-04-02

申请号：US13026904

申请日：2011-02-14

Applicant: Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

Inventor： Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

IPC: G01R19/00 ,  G11C7/00 ,  H03K3/45

CPC classification number: H03K3/356043 ,  H03K3/012 ,  H03K3/35613 ,  H03K3/356182 ,  H03K3/356191 ,  H03M1/002 ,  H03M1/362

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

公开(公告)号：US08401502B2

公开(公告)日：2013-03-19

申请号：US12536024

申请日：2009-08-05

Applicant: Yee Ling Cheung ,  Kevin T. Chan ,  Jan Mulder

Inventor： Yee Ling Cheung ,  Kevin T. Chan ,  Jan Mulder

IPC: H04B1/04

CPC classification number: H04B1/581

Abstract: Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The transmitter includes a plurality of current cells. Each cell is configurable for operating in different modes. The method includes determining a first probability associated with transmitting data at a particular symbolic level and determining a second probability associated with each cell being used during a transmission at the particular symbolic level. Next, one of the modes for each cell is selected in accordance with anticipated performance requirements. An average current of the transmitter is then calculated based upon the determined first and second probabilities and the selected modes.

公开(公告)号：US20120032722A1

公开(公告)日：2012-02-09

申请号：US12881434

申请日：2010-09-14

Applicant: Jan MULDER

Inventor： Jan MULDER

IPC: H03L5/00

CPC classification number: H03F3/45475 ,  H03F3/45192 ,  H03F3/45928 ,  H03F2203/45048 ,  H03F2203/45138 ,  H03F2203/45586 ,  H03M1/1023 ,  H03M1/165

Abstract: An apparatus, a method, and a system are provided to calibrate an offset in an amplifier. The apparatus can include an amplifier, a voltage control unit, a comparator, and a processing unit. The amplifier can have four terminals: a positive differential input (VIN+), a negative differential input (VIN−), a positive differential output (VOUT+), and a negative differential output (VOUT−). The voltage control unit can be configured to adjust a first voltage on VOUT+ and a second voltage on VOUT−. The comparator can be configured to compare the first voltage on VOUT+ to the second voltage on VOUT− when VIN+ and VIN− are coupled to a common voltage. Further, the processing unit can be configured to provide a control signal to the voltage control unit based on the comparison of the first and second voltages on VOUT+ and VOUT−, respectively.

Abstract translation: 提供了一种装置，方法和系统来校准放大器中的偏移。 该装置可以包括放大器，电压控制单元，比较器和处理单元。 放大器可以有四个端子：正差分输入（VIN +），负差分输入（VIN-），正差分输出（VOUT +）和负差分输出（VOUT-））。 电压控制单元可配置为调节VOUT +上的第一电压和VOUT-上的第二电压。 当VIN +和VIN-耦合到公共电压时，比较器可以配置为将VOUT +上的第一个电压与VOUT-上的第二个电压进行比较。 此外，处理单元可以被配置为基于VOUT +和VOUT-上的第一和第二电压的比较来向电压控制单元提供控制信号。

公开(公告)号：US20110133967A1

公开(公告)日：2011-06-09

申请号：US13026904

申请日：2011-02-14

Applicant: Klaas BULT ,  Rudy VAN DE PLASSCHE ,  Jan MULDER

Inventor： Klaas BULT ,  Rudy VAN DE PLASSCHE ,  Jan MULDER

IPC: H03M1/06 ,  H03K3/00 ,  H03K3/02 ,  H03M1/34

CPC classification number: H03K3/356043 ,  H03K3/012 ,  H03K3/35613 ,  H03K3/356182 ,  H03K3/356191 ,  H03M1/002 ,  H03M1/362

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

Abstract translation: 在具有第一极性的双稳态交叉晶体管对和第二极性的第三晶体管的锁存电路中，在锁存电路端口处接收大于偏置电流的电流信号，用第三晶体管放大并施加到 锁存电路端口。 这减小了接收大于偏置电流的电流信号的锁存电路端口达到稳态电压的时间。

公开(公告)号：US20090121910A1

公开(公告)日：2009-05-14

申请号：US12204482

申请日：2008-09-04

Applicant: Yee Ling Cheung ,  Kevin T. Chan ,  Jan Mulder

Inventor： Yee Ling Cheung ,  Kevin T. Chan ,  Jan Mulder

IPC: H03M1/66

CPC classification number: H03F3/45183 ,  H03F2203/45466

Abstract: Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The method includes identifying a phase control signal from an adjacent current cell preceding the particular current cell in time and logically ORing the phase control signal from the preceding cell with a phase control signal from the particular current cell.

Abstract translation: 提供了一种用于控制具有发射机的收发机中的电流特性的方法和系统。 该方法包括在时间上识别来自特定当前小区之前的相邻当前小区的相位控制信号，并且将来自前一小区的相位控制信号与来自特定当前小区的相位控制信号进行逻辑或运算。

公开(公告)号：US07352215B2

公开(公告)日：2008-04-01

申请号：US10649808

申请日：2003-08-28

Applicant: Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

Inventor： Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

IPC: G01R19/00 ,  G11C7/00 ,  H03K3/45

CPC classification number: H03K3/356043 ,  H03K3/012 ,  H03K3/35613 ,  H03K3/356182 ,  H03K3/356191 ,  H03M1/002 ,  H03M1/362

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

Abstract translation: 在具有第一极性的双稳态交叉晶体管对和第二极性的第三晶体管的锁存电路中，在锁存电路端口处接收大于偏置电流的电流信号，用第三晶体管放大并施加到 锁存电路端口。 这减小了接收大于偏置电流的电流信号的锁存电路端口达到稳态电压的时间。

公开(公告)号：US07324038B2

公开(公告)日：2008-01-29

申请号：US10625702

申请日：2003-07-24

Applicant: Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Ruby van de Plassche ,  Marcel Lugthart

Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Ruby van de Plassche ,  Marcel Lugthart

IPC: H03M1/12

CPC classification number: H03M1/146 ,  H03K17/04106 ,  H03M1/204 ,  H03M1/365

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract translation: N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关 两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围 参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出 其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

公开(公告)号：US07135942B2

公开(公告)日：2006-11-14

申请号：US10694952

申请日：2003-10-29

Applicant: Jan R Westra ,  Jan Mulder

Inventor： Jan R Westra ,  Jan Mulder

IPC: H03H7/24 ,  H03G3/10

CPC classification number: H03H7/24

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on. A first switch of the second plurality of switches is turned on, followed by a second switch of second plurality of switches turned off, followed by a third switch of second plurality of switches turned on.

公开(公告)号：US20050093643A1

公开(公告)日：2005-05-05

申请号：US10694952

申请日：2003-10-29

Applicant: Jan Westra ,  Jan Mulder

Inventor： Jan Westra ,  Jan Mulder

IPC: H01P1/22 ,  H03H7/24

CPC classification number: H03H7/24

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on. A first switch of the second plurality of switches is turned on, followed by a second switch of second plurality of switches turned off, followed by a third switch of second plurality of switches turned on.

Abstract translation: 可编程增益衰减器包括终端电阻。 第一终端开关将终端电阻器的一侧连接到第一输出。 第二终端开关将终端电阻器的另一侧连接到第二输出端。 在第一输入和终端电阻的第一侧之间布置第一电阻梯。 第一多个开关将来自第一电阻梯的相应抽头连接到第一输出。 在第二输入端和终端电阻器的第二侧之间布置第二电阻梯。 第二多个开关将来自第二电阻梯的相应抽头连接到第二输出。 第一多个开关的第一开关被接通，接着是第一多个开关的第二开关被关闭，随后开启第一组开关的第三开关。 第二多个开关的第一开关被接通，随后是第二多个开关的第二开关被关闭，随后是第二多个开关的第三开关导通。