公开(公告)号：US20070052030A1

公开(公告)日：2007-03-08

申请号：US11222707

申请日：2005-09-08

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

IPC: H01L23/62

CPC classification number: H01L27/0262

Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.

Abstract translation: 提供具有寄生可控硅整流器（SCR）结构和可控保持电流的静电放电（ESD）器件。 在第一N +掺杂区域和第一P +掺杂区域之间保持第一距离，并且在第二P +掺杂区域和第三N +掺杂区域之间保持第二距离。 此外，通过调制第一距离和第二距离，可以将ESD装置的保持电流设定为特定值。 保持电流与第一距离和第二距离成反比。

公开(公告)号：US20060220170A1

公开(公告)日：2006-10-05

申请号：US11096959

申请日：2005-03-31

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu Lin ,  Ta-yung Yang

IPC: H01L29/00

CPC classification number: H01L21/823493 ,  H01L21/823418 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

Abstract: A high-voltage MOSFET having isolation structure is provided. An N-type MOSFET includes a first deep N-type well. A first P-type region is formed in the first deep N-type well to enclose a first source region and a first contact region. A first drain region is formed in the first deep N-type well. A P-type MOSFET includes a second deep N-type well. A second P-type region is formed in the second deep N-type well to enclose a second drain region. A second source region and a second contact region are formed in the second deep N-type well. A polysilicon gate oxidation layer is disposed above the thin gate oxidation layer and the thick field oxidation layer to control the current in the channel of the MOSFET. Separated P-type regions provide further isolation between MOSFETs. A first gap and a second gap increase the breakdown voltage of the high-voltage MOSFET.

Abstract translation: 提供了具有隔离结构的高压MOSFET。 N型MOSFET包括第一深N型阱。 在第一深N型阱中形成第一P型区域以包围第一源极区域和第一接触区域。 在第一深N型阱中形成第一漏区。 P型MOSFET包括第二深N型阱。 在第二深N型阱中形成第二P型区域以包围第二漏极区域。 在第二深N型阱中形成第二源区和第二接触区。 多晶硅栅极氧化层设置在薄栅氧化层和厚场氧化层之上，以控制MOSFET沟道中的电流。 分离的P型区域提供MOSFET之间的进一步隔离。 第一间隙和第二间隙增加了高压MOSFET的击穿电压。

公开(公告)号：US20060033156A1

公开(公告)日：2006-02-16

申请号：US10919916

申请日：2004-08-16

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

IPC: H01L29/76

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/42368

Abstract: A high voltage LDMOS transistor according to the present invention includes at least one P-field block in the extended drain region of the N-well. The P-field blocks form junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The source region and P-field blocks enclose the drain region, which makes the LDMOS transistor self-isolated.

公开(公告)号：US20050146903A1

公开(公告)日：2005-07-07

申请号：US10752363

申请日：2004-01-05

Applicant: Ta-Yung Yang ,  Chern-Lin Chen ,  Jenn-Yu Lin ,  Guo-Kiang Hung

Inventor： Ta-Yung Yang ,  Chern-Lin Chen ,  Jenn-Yu Lin ,  Guo-Kiang Hung

IPC: H02M3/335

CPC classification number: H02M3/33507 ,  H01F2038/026

Abstract: The present invention demonstrates a power-mode controlled power converter for supplying a constant output voltage and a constant output current. A PWM controller of the power-mode controlled power converter generates a PWM signal in response to the voltage sampled from a transformer auxiliary winding. A programmable current-sink and a detection resistor compensate for the voltage drop of an output rectifier. A low-pass filter integrates a switching-current voltage to an average-current signal. An attenuator produces an input-voltage signal from a line-voltage input signal. The PWM controller multiplies the average-current signal with the input-voltage signal to generate a power-control signal. An error-amplifier compares the power-control signal with a power-reference voltage to generate a limit voltage. The limit voltage controls the power delivered from a primary-side circuit to a secondary-side circuit of the power-mode controlled power converter. Since the power-reference voltage varies in proportional to output voltage variations, a constant output current is therefore achieved.

Abstract translation: 本发明示出了用于提供恒定输出电压和恒定输出电流的功率模式控制功率转换器。 功率模式受控功率转换器的PWM控制器响应于从变压器辅助绕组采样的电压产生PWM信号。 可编程电流吸收器和检测电阻器补偿输出整流器的电压降。 低通滤波器将开关电流电压集成到平均电流信号。 衰减器从线电压输入信号产生输入电压信号。 PWM控制器将平均电流信号与输入电压信号相乘以产生功率控制信号。 误差放大器将功率控制信号与功率参考电压进行比较，以产生极限电压。 极限电压控制从功率模式受控功率转换器的初级侧电路到次级侧电路的功率。 由于功率参考电压与输出电压变化成比例变化，因此实现恒定的输出电流。

公开(公告)号：US20050024897A1

公开(公告)日：2005-02-03

申请号：US10629150

申请日：2003-07-28

Applicant: Ta-Yung Yang ,  Jenn-Yu Lin ,  Chern-Lin Chen

Inventor： Ta-Yung Yang ,  Jenn-Yu Lin ,  Chern-Lin Chen

IPC: H02M1/38 ,  H02M3/335

CPC classification number: H02M1/38 ,  H02M3/33592 ,  Y02B70/1475

Abstract: The present invention provides a forward power converter with a synchronized rectifying controller. The synchronized rectifying controller has a detection input for detecting the voltage of a secondary winding of a transformer, and thereby accurately measuring the PWM signal. Based on this measurement, the synchronized rectifying controller generates control signals for two secondary-side rectifying MOSFETs. The present invention also introduces a delay time using a timing resistor coupled to the synchronized rectifying controller. This avoids cross-conduction from secondary-side MOSFETs. The present invention also includes an output current-sense mechanism to avoid reverse inductor currents under light-load conditions.

Abstract translation: 本发明提供一种具有同步整流控制器的正向功率转换器。 同步整流控制器具有用于检测变压器的次级绕组的电压的检测输入，从而精确地测量PWM信号。 基于该测量，同步整流控制器产生用于两个次级侧整流MOSFET的控制信号。 本发明还引入使用耦合到同步整流控制器的定时电阻器的延迟时间。 这避免了二次侧MOSFET的交叉导通。 本发明还包括在轻负载条件下避免反向电感电流的输出电流检测机构。

公开(公告)号：US20070004150A1

公开(公告)日：2007-01-04

申请号：US11427773

申请日：2006-06-29

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-yu Lin ,  Ta-yung Yang

IPC: H01L21/8234 ,  H01L23/62

CPC classification number: H01L27/0259

Abstract: An electrostatic discharge (ESD) protection device with adjustable single-trigger or multi-trigger voltage is provided. The semiconductor structure has multi-stage protection semiconductor circuit finction and adjustable discharge capacity. The single-trigger or multi-trigger semiconductor structure may be fabricated by using the conventional semiconductor process, and can be applied to IC semiconductor design and to effectively protect the important semiconductor devices and to prevent the semiconductor devices from ESD damage. In particular, the present invention can meet the requirements of high power semiconductor device and has better protection function compared to conventional ESD protection circuit. In the present invention, a plurality of N-wells or P-wells connected in parallel are used to adjust the discharge capacity of various wells in the P-substrate so as to improve the ESD protection capability and meet different power standards.

Abstract translation: 提供具有可调单触发或多触发电压的静电放电（ESD）保护装置。 半导体结构具有多级保护半导体电路的功能和可调放电容量。 单触发或多触发半导体结构可以通过使用传统的半导体工艺制造，并且可以应用于IC半导体设计并且有效地保护重要的半导体器件并且防止半导体器件受到ESD损坏。 特别地，本发明可以满足大功率半导体器件的要求，与传统的ESD保护电路相比具有更好的保护功能。 在本发明中，使用并联连接的多个N阱或P阱来调整P基板中的各个阱的放电容量，以提高ESD保护能力并满足不同的功率标准。

公开(公告)号：US20060056204A1

公开(公告)日：2006-03-16

申请号：US10943318

申请日：2004-09-16

Applicant: Ta-yung Yang ,  Guo-Kiang Hung ,  Jenn-yu Lin ,  Chuh-Ching Li ,  Shao-Wei Chiu

Inventor： Ta-yung Yang ,  Guo-Kiang Hung ,  Jenn-yu Lin ,  Chuh-Ching Li ,  Shao-Wei Chiu

IPC: H02M5/27

CPC classification number: H02M3/33507

Abstract: The present invention discloses a switching control circuit for a primary-side controlled power converter. A voltage-waveform detector produces a voltage-feedback signal and a discharge-time signal. A current-waveform detector generates a current-waveform signal by measuring a primary-side switching current. An integrator generates a current-feedback signal by integrating the current-waveform signal with the discharge time. A time constant of the integrator is correlated with the switching frequency, thus the current-feedback signal is proportional to an output current of the power converter. A PWM circuit controls the pulse width of the switching signal in response to the outputs of a voltage-loop error amplifier and a current-loop error amplifier. The output voltage and the maximum output current of the power converter are therefore regulated.

Abstract translation: 本发明公开了一种用于初级侧受控电力转换器的开关控制电路。 电压波形检测器产生电压反馈信号和放电时间信号。 电流波形检测器通过测量初级侧开关电流产生电流波形信号。 积分器通过将电流波形信号与放电时间进行积分来产生电流反馈信号。 积分器的时间常数与开关频率相关，因此电流反馈信号与功率转换器的输出电流成比例。 PWM电路响应于电压环路误差放大器和电流环路误差放大器的输出来控制开关信号的脉冲宽度。 因此调节功率转换器的输出电压和最大输出电流。

公开(公告)号：US07847365B2

公开(公告)日：2010-12-07

申请号：US11913037

申请日：2005-10-14

Applicant: Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-yung Yang

Inventor： Chih-Feng Huang ,  Tuo-Hsin Chien ,  Jenn-Yu Lin ,  Ta-yung Yang

IPC: H01L29/78

CPC classification number: H01L27/0928 ,  H01L21/823878 ,  H01L21/823892

Abstract: A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors.

Abstract translation: 提供了具有用于单片集成的隔离结构的MOSFET器件。 P型MOSFET包括设置在P型衬底中的第一N阱，设置在第一N阱中的第一P型区，设置在第一P型区中的P +漏极区，第一源电极 形成有P +源极区域和N +接触区域。 第一个N阱围绕着P +源极区域和N +接触区域。 N型MOSFET包括设置在P型衬底中的第二N阱，设置在第二N阱中的第二P型区，设置在第二N阱中的N +漏极区，第二源电极 形成有N +源区和P +接触区。 第二P型区围绕N +源区和P +接触区。 多个分离的P型区域设置在P型衬底中以提供晶体管的隔离。

公开(公告)号：US20070178648A1

公开(公告)日：2007-08-02

申请号：US11682621

申请日：2007-03-06

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

IPC: H01L21/8234

CPC classification number: H01L21/823814 ,  H01L21/823857 ,  H01L21/823892

Abstract: A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.

Abstract translation: 一种制造不同电压装置的方法主要包括在高电压装置区域中形成至少一个高电压阱，在低电压装置区域中形成至少一个N阱，在低电压装置区域中形成至少一个P阱 ，高压器件区域中的源/漏极阱以及p型衬底中的隔离区中的隔离阱。 通过调制离子掺杂分布来调整击穿电压。 此外，调整注入导电离子的参数，以将导电离子注入到高电压器件区域和低电压器件区域中。 在器件之间的隔离区域中形成的隔离阱用于在高电压器件区域上形成的分离器件和在低电压器件区域上形成的器件。 HV栅极氧化物层的厚度比用于调制高电压器件和低电压器件的阈值电压的LV栅极氧化物层的厚度厚。

公开(公告)号：US20070052032A1

公开(公告)日：2007-03-08

申请号：US11223745

申请日：2005-09-08

Applicant: Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

Inventor： Chih-Feng Huang ,  Ta-yung Yang ,  Jenn-yu Lin ,  Tuo-Hsin Chien

IPC: H01L23/62

CPC classification number: H01L27/0262 ,  H01L27/0921

Abstract: An electrostatic discharge (ESD) device with latch-up immunity is provided. The ESD device has an equivalent SCR structure when a supply voltage is not applied thereto and has an equivalent PN diode structure when the supply voltage is applied thereto, thus freeing the ESD device from the latch-up phenomenon.

Abstract translation: 提供具有闭锁抑制的静电放电（ESD）器件。 当不施加电源电压时，ESD器件具有等效的SCR结构，并且当施加电源电压时具有等效的PN二极管结构，从而使ESD器件免于闩锁现象。