公开(公告)号：US20070089030A1

公开(公告)日：2007-04-19

申请号：US11241356

申请日：2005-09-30

Applicant: Alejandro Beracoechea ,  Jing Ling

Inventor： Alejandro Beracoechea ,  Jing Ling

IPC: H03M13/00

CPC classification number: H04L49/9073 ,  H04L49/90

Abstract: An apparatus and a method for flexibly configuring memory bandwidth allocations for different data channels is described. In one embodiment, the invention includes receiving data from a data communications channel, storing the data in a buffer, upon accumulating a predefined amount of data from the channel, determining a base address of a partition of a memory associated with the data communications channel, and storing a burst of the stored data in the memory partition.

Abstract translation: 描述了用于灵活地配置用于不同数据信道的存储器带宽分配的装置和方法。 在一个实施例中，本发明包括从数据通信信道接收数据，在从信道累积预定量的数据之后，将数据存储在缓冲器中，确定与数据通信信道相关联的存储器的分区的基地址， 以及将存储的数据的突发存储在存储器分区中。

公开(公告)号：US20070086479A1

公开(公告)日：2007-04-19

申请号：US11359819

申请日：2006-02-21

Applicant: Jing Ling ,  Jean-Michel Caia ,  Alejandro Beracoechea

Inventor： Jing Ling ,  Jean-Michel Caia ,  Alejandro Beracoechea

IPC: H04L12/66

CPC classification number: H04L49/9073 ,  H04L49/90

Abstract: Techniques are described herein that may be used to buffer traffic received at a communications device. For example, a buffer external from a traffic processor may be used to buffer traffic in ingress or egress directions. For example, a bandwidth in each of directions of to and from the buffer may be less than a sum of maximum bandwidths in ingress and egress directions. For example, a single memory interface may be used to communicatively couple the buffer and the traffic processor.

Abstract translation: 本文描述了可用于缓冲在通信设备处接收的业务的技术。 例如，可以使用来自业务处理器的外部缓冲器来缓冲入口或出口方向上的流量。 例如，往返缓冲器的每个方向上的带宽可以小于入口和出口方向上的最大带宽之和。 例如，可以使用单个存储器接口来通信地耦合缓冲器和流量处理器。

公开(公告)号：US07061867B2

公开(公告)日：2006-06-13

申请号：US10115229

申请日：2002-04-02

Applicant: Anguo T. Huang ,  Jing Ling ,  Jean-Michel Caia ,  Juan-Carlos Calderon ,  Vivek Joshi

Inventor： Anguo T. Huang ,  Jing Ling ,  Jean-Michel Caia ,  Juan-Carlos Calderon ,  Vivek Joshi

IPC: H04J1/16 ,  H04L1/00 ,  H04L12/26 ,  G01R31/08

CPC classification number: H04L47/6215 ,  H04L47/10 ,  H04L47/39 ,  H04L47/50 ,  H04L47/521 ,  H04L47/627

Abstract: The rate-based scheduling for a network application is used to control the bandwidth available to a flow while scheduling the transmission of the flow. The rate-based scheduling uses rate credits to represent the amount of data a flow is permitted to transmit and only permits a flow to transmit if the flow has rate credit available. A flow is permitted to transmit only if the peak packet rate for the scheduler has not been exceeded.

公开(公告)号：US07939671B2

公开(公告)日：2011-05-10

申请号：US12222918

申请日：2008-08-19

Applicant: Xiaodong Li ,  Andrew Patron ,  Catherine Tachdjian ,  Hong Xu ,  Qing Li ,  Alexey Pronin ,  Guy Servant ,  Lan Zhang ,  Thomas Brady ,  Vincent Darmohusodo ,  Melissa Arellano ,  Victor Selchau ,  Brett Weylan Ching ,  Donald S. Karanewsky ,  Paul Brust ,  Jing Ling ,  Wen Zhao ,  Chad Priest

Inventor： Xiaodong Li ,  Andrew Patron ,  Catherine Tachdjian ,  Hong Xu ,  Qing Li ,  Alexey Pronin ,  Guy Servant ,  Lan Zhang ,  Thomas Brady ,  Vincent Darmohusodo ,  Melissa Arellano ,  Victor Selchau ,  Brett Weylan Ching ,  Donald S. Karanewsky ,  Paul Brust ,  Jing Ling ,  Wen Zhao ,  Chad Priest

IPC: C07D261/08 ,  C07D413/14 ,  A61K31/44 ,  A61K31/42

CPC classification number: C07C311/17 ,  A23L27/86 ,  A61K8/46 ,  A61K8/466 ,  A61K8/4933 ,  A61K8/494 ,  A61K8/4973 ,  A61K8/498 ,  A61K8/4986 ,  A61K31/135 ,  A61K31/4439 ,  A61K31/485 ,  A61K31/60 ,  A61K31/704 ,  A61K45/06 ,  A61Q11/00 ,  C07C233/73 ,  C07C311/04 ,  C07C311/13 ,  C07C311/16 ,  C07C311/18 ,  C07C311/19 ,  C07C311/20 ,  C07C311/21 ,  C07C311/29 ,  C07C311/46 ,  C07C323/49 ,  C07C335/16 ,  C07C335/18 ,  C07D213/42 ,  C07D213/71 ,  C07D217/08 ,  C07D223/18 ,  C07D307/14 ,  C07D307/52 ,  C07D317/58 ,  C07D333/20 ,  C07D333/34 ,  A61K2300/00

Abstract: The present invention relates to the discovery that specific human taste receptors in the T2R taste receptor family respond to particular bitter compounds present in, e.g., coffee. Also, the invention relates to the discovery of specific compounds and compositions containing that function as bitter taste blockers and the use thereof as bitter taste blockers or flavor modulators in, e.g., coffee and coffee flavored foods, beverages and medicaments. Also, the present invention relates to the discovery of a compound that antagonizes numerous different human T2Rs and the use thereof in assays and as a bitter taste blocker in compositions for ingestion by humans and animals.

Abstract translation: 本发明涉及T2R味觉受体家族中的特定人味受体对存在于例如咖啡中的特定苦味化合物的反应的发现。 此外，本发明涉及含有作为苦味抑制剂的特定化合物和组合物的发现，以及其作为例如咖啡和咖啡风味食品，饮料和药物中的苦味抑制剂或风味调节剂的用途。 此外，本发明涉及一种拮抗多种不同人类T2R的化合物的发现及其在测定中的用途以及用于摄取人类和动物的组合物中的苦味阻滞剂。

公开(公告)号：US07564777B2

公开(公告)日：2009-07-21

申请号：US11129169

申请日：2005-05-13

Applicant: Soowan Suh ,  Jing Ling ,  Juan-Carlos Calderon ,  Jean-Michel Caia

Inventor： Soowan Suh ,  Jing Ling ,  Juan-Carlos Calderon ,  Jean-Michel Caia

IPC: H04L1/00 ,  H04L12/28 ,  H04J1/16 ,  H04J3/14

CPC classification number: H04J3/14 ,  H04J3/062 ,  H04J2203/006 ,  H04J2203/0069 ,  H04J2203/0094 ,  Y10S370/907

Abstract: In a communication system that uses virtually concatenated payloads, techniques to determine when to declare and when to clear alarm indication signal (AIS) for a group. The declaration of AIS for a group may occur based on when declaration of AIS for a member of a group occurs. The clearing of group AIS may occur based on when clearing of AIS by a last member of a group to clear AIS occurs.

Abstract translation: 在使用虚拟级联有效载荷的通信系统中，确定何时声明的技术以及何时清除组的报警指示信号（AIS）。 基于组成员的AIS声明发生时，可能会发生AIS的声明。 基于AIS的清除，可以根据组中的最后一个成员清除AIS来清除AIS。

公开(公告)号：US07298744B1

公开(公告)日：2007-11-20

申请号：US10749542

申请日：2003-12-30

Applicant: Soowan Suh ,  Jing Ling ,  Juan-Carlos Calderon ,  Jean-Michel Caia

Inventor： Soowan Suh ,  Jing Ling ,  Juan-Carlos Calderon ,  Jean-Michel Caia

IPC: H04L12/28 ,  H04L12/56

CPC classification number: H04J3/1611 ,  H04J2203/0094 ,  H04J2203/0096 ,  H04Q2213/13367 ,  Y10S370/907

Abstract: A method and apparatus for processing at least two types of payloads received at varying intervals in a communications network using a single processing path is provided. The two types of payloads may include virtually and contiguously concatenated payloads according to SONET/SHD architecture. The method comprises assigning pseudo indices to payloads having no indices associated therewith and providing both sets of payloads, including indices and pseudo indices, to the single processing path.

Abstract translation: 提供一种用于处理在使用单个处理路径的通信网络中以不同间隔接收的至少两种类型的有效载荷的方法和装置。 两种类型的有效载荷可以包括根据SONET / SHD架构的虚拟和连续的级联有效载荷。 该方法包括将伪索引分配给没有与其相关联的索引的有效载荷，并向单个处理路径提供包括索引和伪索引的两组有效载荷。

公开(公告)号：US20060221944A1

公开(公告)日：2006-10-05

申请号：US11093907

申请日：2005-03-30

Applicant: Jing Ling ,  Soowan Suh ,  Juan-Carlos Calderon

Inventor： Jing Ling ,  Soowan Suh ,  Juan-Carlos Calderon

IPC: H04L12/50

CPC classification number: G06F12/06 ,  H04J3/0623 ,  H04J2203/0094 ,  H04L45/742 ,  H04L49/30 ,  H04L49/90 ,  H04L49/901

Abstract: In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.

公开(公告)号：US07065628B2

公开(公告)日：2006-06-20

申请号：US10158409

申请日：2002-05-29

Applicant: Juan-Carlos Calderon ,  Jing Ling ,  Jean-Michel Caia ,  Vivek Joshi ,  Anguo T. Huang

Inventor： Juan-Carlos Calderon ,  Jing Ling ,  Jean-Michel Caia ,  Vivek Joshi ,  Anguo T. Huang

IPC: G06F12/00

CPC classification number: H04L49/103 ,  H04L49/109 ,  H04L49/254

Abstract: Memory access efficiency for packet applications may be improved by transferring full partitions of data. The number of full partitions written to external memory may be increased by temporarily storing packets using on-chip memory that is on a chip with the processor. Before writing packets to external memory, packets of length smaller than the external memory partition size may be temporarily stored in the on-chip memory until an amount corresponding to a full or nearly full partition has been collected, at which point the data can be efficiently written to an external memory partition.

公开(公告)号：US06944728B2

公开(公告)日：2005-09-13

申请号：US10329283

申请日：2002-12-23

Applicant: Juan-Carlos Calderon ,  Jean-Michel Caia ,  Vivek Joshi ,  Jing Ling ,  Anguo T. Huang

Inventor： Juan-Carlos Calderon ,  Jean-Michel Caia ,  Vivek Joshi ,  Jing Ling ,  Anguo T. Huang

IPC: G06F12/00 ,  H04L12/56

CPC classification number: H04L49/103

Abstract: Interleaving memory access includes enabling data included in a receive flow of data to be stored in a first memory bank, enabling data included in a transmit flow of data to be stored in a second memory bank, and alternating access of data in the first memory bank with access of data in the second memory bank.

Abstract translation: 交错存储器访问包括允许包含在接收数据流中的数据被存储在第一存储体中，使包含在数据传输流中的数据能够存储在第二存储体中，以及交替访问第一存储体中的数据 具有访问第二存储体中的数据。

公开(公告)号：US06433017B1

公开(公告)日：2002-08-13

申请号：US09796340

申请日：2001-02-28

Applicant: Philip L. Felgner ,  Xiang Gao ,  Jing Ling

Inventor： Philip L. Felgner ,  Xiang Gao ,  Jing Ling

IPC: A61K3116

CPC classification number: C07C271/20 ,  C07C217/22 ,  C07C237/22 ,  C07C311/19 ,  C07C311/64 ,  Y02P20/55

Abstract: In accordance with the present invention, there are provided amphiphilic polyamine compounds and derivatives thereof having the property of promoting transfection of polynucleotides and polypeptides into cells, and formulations comprising said compounds.

Abstract translation: 根据本发明，提供具有促进将多核苷酸和多肽转染入细胞的性质的二亲多胺化合物及其衍生物，以及包含所述化合物的制剂。