公开(公告)号：US20120062406A1

公开(公告)日：2012-03-15

申请号：US12982531

申请日：2010-12-30

申请人： Young Kyun Cho ,  Young-deuk Jeon ,  Jaewon Nam ,  Jong-Kee Kwon

发明人： Young Kyun Cho ,  Young-deuk Jeon ,  Jaewon Nam ,  Jong-Kee Kwon

IPC分类号： H03M1/36 ,  H03M1/12

CPC分类号： H03M1/145 ,  H03M1/365 ,  H03M1/468

摘要： Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal.

摘要翻译： 提供了一种消耗低功耗并保证快速操作特性的模拟数字转换装置。 模拟数字转换装置包括子ADC和逐次逼近ADC。 子ADC通过使用第一和第二参考电压将外部模拟信号转换为第一数字信号。 逐次逼近ADC包括多个比特流，并且根据使用第一和第二参考电压的逐次逼近操作将外部模拟信号转换为第二数字信号。 逐次逼近ADC接收第一数字信号，并且在第一和第二参考电压中的一个被基于第一数字信号施加到比特流的状态下转换第二数字信号。

公开(公告)号：US08040156B2

公开(公告)日：2011-10-18

申请号：US12466283

申请日：2009-05-14

申请人： Hui Dong Lee ,  Kwi Dong Kim ,  Jong Kee Kwon

发明人： Hui Dong Lee ,  Kwi Dong Kim ,  Jong Kee Kwon

IPC分类号： H03K5/19

CPC分类号： H03L7/095

摘要： Provided are a lock detection circuit and a lock detecting method. The lock detection circuit includes two delay devices, four flip-flops and two logic gates, and can accurately detect a lock state of a phase locked loop (PLL) circuit. Therefore, the lock detection circuit can be implemented in a simple structure, and as a result, the lock detection circuit can be compact in size and can consume less electric power. Also, the lock detecting method enables lock detection process to be simpler, so that a lock state can be detected within a short time period.

摘要翻译： 提供锁定检测电路和锁定检测方法。 锁定检测电路包括两个延迟器件，四个触发器和两个逻辑门，并且可以精确地检测锁相环（PLL）电路的锁定状态。 因此，可以以简单的结构实现锁定检测电路，结果，锁定检测电路的尺寸可以小巧，并且可以消耗更少的电力。 此外，锁定检测方法使得锁定检测处理更简单，从而可以在短时间内检测锁定状态。

公开(公告)号：US20110153878A1

公开(公告)日：2011-06-23

申请号：US12882141

申请日：2010-09-14

申请人： Ik Jae CHUN ,  Chun Gi Lyuh ,  Se Wan Heo ,  Sang Hun Yoon ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Ik Jae CHUN ,  Chun Gi Lyuh ,  Se Wan Heo ,  Sang Hun Yoon ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.

摘要翻译： 提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。 存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道 控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。

公开(公告)号：US20110148485A1

公开(公告)日：2011-06-23

申请号：US12882132

申请日：2010-09-14

申请人： Sang Hyun CHO ,  Hui Dong Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Seung Tak Ryu

发明人： Sang Hyun CHO ,  Hui Dong Lee ,  Kwi Dong Kim ,  Jong Kee Kwon ,  Seung Tak Ryu

IPC分类号： H03L7/06

CPC分类号： H03L7/0995 ,  H03L7/099 ,  H03L2207/06

摘要： A phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO) with a variable gain is provided. A phase frequency detector (PFD) detects a phase difference between a reference signal and a PLL feedback signal. A charge pump and a loop filter sequentially process an output signal of the PFD. A VCO has different gains according to a mode transition. A control voltage applied to the VCO is selected from an output signal of the loop filter and an additional control signal according to the mode transition.

摘要翻译： 提供了包括具有可变增益的压控振荡器（VCO）的锁相环（PLL）电路。 相位频率检测器（PFD）检测参考信号和PLL反馈信号之间的相位差。 电荷泵和环路滤波器依次处理PFD的输出信号。 根据模式转换，VCO具有不同的增益。 根据模式转换，从环路滤波器的输出信号和附加控制信号中选择施加到VCO的控制电压。

公开(公告)号：US07821341B2

公开(公告)日：2010-10-26

申请号：US12507701

申请日：2009-07-22

申请人： Yi Gyeong Kim ,  Min Hyung Cho ,  Jong Kee Kwon

发明人： Yi Gyeong Kim ,  Min Hyung Cho ,  Jong Kee Kwon

IPC分类号： H03G3/10

CPC分类号： H03F3/45475 ,  H03F2203/45528 ,  H03F2203/45591

摘要： Provided are a gain control device and an amplifier using the gain control device. The gain control device includes a first input resistance unit having a first variable resistor whose resistance is linearly variable and a first fixed resistor respectively receiving a first input signal and a second input signal having a sign different from the first input signal and outputting current through a first output terminal, and a second input resistance unit having a second fixed resistor and a second variable resistor whose resistance is linearly variable respectively receiving the first input signal and the second input signal and outputting current through a second output terminal.Since the gain control device can separately perform dB-linear gain control, it is easily combined with a circuit, such as a continuous-time sigma-delta modulator (SDM), a continuous-time filter, and a continuous-time analog-to-digital converter (ADC), and enables miniaturization and low power consumption.

摘要翻译： 提供了增益控制装置和使用增益控制装置的放大器。 所述增益控制装置包括具有电阻为线性变化的第一可变电阻器和分别接收第一输入信号的第一固定电阻器和具有与第一输入信号不同的符号的第二输入信号的第一输入电阻单元， 第一输出端子和具有第二固定电阻器和第二可变电阻器的第二输入电阻单元，其电阻为线性变化，分别接收第一输入信号和第二输入信号，并通过第二输出端子输出电流。 由于增益控制装置可以单独执行dB线性增益控制，所以可以容易地与诸如连续时间Σ-Δ调制器（SDM），连续时间滤波器以及连续时间模拟到 数字转换器（ADC），并实现小型化和低功耗。

公开(公告)号：US20090128230A1

公开(公告)日：2009-05-21

申请号：US12195260

申请日：2008-08-20

申请人： Jeong Jin Roh ,  Hyung Dong Roh ,  Hyoung-Joong Kim ,  Yi Gyeong Kim ,  Jong Kee Kwon

发明人： Jeong Jin Roh ,  Hyung Dong Roh ,  Hyoung-Joong Kim ,  Yi Gyeong Kim ,  Jong Kee Kwon

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： Provided is a band-gap reference voltage generator for low-voltage operation and high precision. The band-gap reference voltage generator minimizes voltage drop by connecting resistors in parallel to bipolar transistors, and cancels temperature dependence by properly adjusting a resistor of an output stage, so that it can provide a stable reference voltage that is unaffected by a change in temperature in spite of a low power supply voltage. Further, the band-gap reference voltage generator minimizes variation of the reference voltage caused by offset noise by switching of input and output voltages at input and output stages of a feedback amplifier, so that it can provide a precise reference voltage.

摘要翻译： 提供一种用于低电压操作和高精度的带隙参考电压发生器。 带隙参考电压发生器通过将电阻并联连接到双极晶体管来最小化电压降，并通过适当调整输出级的电阻来消除温度依赖性，从而可以提供不受温度变化影响的稳定参考电压 尽管电源电压低。 此外，带隙参考电压发生器通过切换反馈放大器的输入和输出级的输入和输出电压来最小化由偏移噪声引起的参考电压的变化，使得其可以提供精确的参考电压。

公开(公告)号：US07482966B2

公开(公告)日：2009-01-27

申请号：US11946583

申请日：2007-11-28

申请人： Seung Chul Lee ,  Young Deuk Jeon ,  Kwi Dong Kim ,  Jong Kee Kwon

发明人： Seung Chul Lee ,  Young Deuk Jeon ,  Kwi Dong Kim ,  Jong Kee Kwon

IPC分类号： H03M1/38

CPC分类号： H03M1/0678 ,  H03M1/162

摘要： Provided is an algorithm analog-to-digital converter (ADC). The algorithm ADC obtains two digital outputs through different capacitor connections for one analog input signal and adds the digital output signals to obtain a final output value, so that a mismatch factor of the capacitor is removed to minimize a linearity limitation resulting from the capacitor mismatch. In addition, the algorithm ADC minimizes power consumption by making the operating frequency slow at a cycle requiring a high resolution and making the operating frequency fast at a cycle requiring a low resolution, i.e., outputting different operating clock frequencies according to a required resolution.

摘要翻译： 提供了一种算法模数转换器（ADC）。 算法ADC通过不同的电容器连接获得两个数字输出，用于一个模拟输入信号，并将数字输出信号相加以获得最终输出值，从而消除电容器的失配因子，以最小化由电容器失配引起的线性限制。 此外，算法ADC通过使工作频率在需要高分辨率的周期中变慢，并使工作频率在需要低分辨率的周期（即，根据所需分辨率输出不同的工作时钟频率）的情况下将功率消耗最小化。

公开(公告)号：US20080136699A1

公开(公告)日：2008-06-12

申请号：US11946583

申请日：2007-11-28

申请人： Seung Chul LEE ,  Young Deuk JEON ,  Kwi Dong KIM ,  Jong Kee KWON

发明人： Seung Chul LEE ,  Young Deuk JEON ,  Kwi Dong KIM ,  Jong Kee KWON

IPC分类号： H03M1/38

CPC分类号： H03M1/0678 ,  H03M1/162

摘要： Provided is an algorithm analog-to-digital converter (ADC). The algorithm ADC obtains two digital outputs through different capacitor connections for one analog input signal and adds the digital output signals to obtain a final output value, so that a mismatch factor of the capacitor is removed to minimize a linearity limitation resulting from the capacitor mismatch. In addition, the algorithm ADC minimizes power consumption by making the operating frequency slow at a cycle requiring a high resolution and making the operating frequency fast at a cycle requiring a low resolution, i.e., outputting different operating clock frequencies according to a required resolution.

摘要翻译： 提供了一种算法模数转换器（ADC）。 算法ADC通过不同的电容器连接获得两个数字输出，用于一个模拟输入信号，并将数字输出信号相加以获得最终输出值，从而消除电容器的失配因子，以最小化由电容器失配引起的线性限制。 此外，算法ADC通过使工作频率在需要高分辨率的周期中变慢，并使工作频率在需要低分辨率的周期（即，根据所需分辨率输出不同的工作时钟频率）的情况下将功率消耗最小化。

公开(公告)号：US07180358B2

公开(公告)日：2007-02-20

申请号：US11004432

申请日：2004-12-03

申请人： Jong Kee Kwon ,  Mun Yang Park ,  Jong Dae Kim ,  Won Chul Song

发明人： Jong Kee Kwon ,  Mun Yang Park ,  Jong Dae Kim ,  Won Chul Song

IPC分类号： G06G7/20

CPC分类号： H03F3/45928 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2203/45212 ,  H03F2203/45482 ,  H03F2203/45484 ,  H03F2203/45508 ,  H03G7/001

摘要： Provided is a CMOS exponential function generating circuit capable of compensating for the exponential function characteristic according to temperature variations. The exponential function generating circuit includes an voltage scaler scaling the value of an external gain control voltage signal, an exponential function generating unit generating exponential function current and voltage in response to a signal output from the voltage scaler, a reference voltage generator providing a reference voltage to the exponential function generating unit, and a temperature compensator compensating for the exponential function characteristic according to temperature variations.

摘要翻译： 提供了能够根据温度变化补偿指数函数特性的CMOS指数函数发生电路。 指数函数发生电路包括缩放外部增益控制电压信号的值的电压缩放器，响应于从电压调节器输出的信号产生指数函数电流和电压的指数函数产生单元，提供参考电压的参考电压发生器 到指数函数产生单元，以及根据温度变化补偿指数函数特性的温度补偿器。

公开(公告)号：US06833766B2

公开(公告)日：2004-12-21

申请号：US10410829

申请日：2003-04-09

申请人： Kwi-dong Kim ,  Jong-kee Kwon ,  Hee-bum Jung ,  Kyung-soo Kim

发明人： Kwi-dong Kim ,  Jong-kee Kwon ,  Hee-bum Jung ,  Kyung-soo Kim

IPC分类号： H03L700

CPC分类号： H03L1/00 ,  H03L7/0995

摘要： There is provided an adaptive loop gain control circuit for a voltage-controlled oscillator (VCO). The adaptive loop gain control circuit for a voltage-controlled oscillator (VCO) includes a detected voltage generating unit which generates a detected voltage signal according to changes in an operating voltage and an operating temperature, and a control circuit unit which outputs an oscillation control current signal according to the detected voltage signal and an input control voltage signal. The adaptive loop gain control circuit for a voltage-controlled oscillator (VCO) compensates for an oscillation control current according to changes in operating voltage and temperature and compensates for the gain of a phase locked loop (PLL) system, thereby ensuring high operating stability in the PLL circuit.

摘要翻译： 提供了一种用于压控振荡器（VCO）的自适应环路增益控制电路。 用于压控振荡器（VCO）的自适应环路增益控制电路包括：检测电压产生单元，其根据工作电压和工作温度的变化产生检测的电压信号;以及控制电路单元，其输出振荡控制电流 信号根据检测到的电压信号和输入控制电压信号。 用于压控振荡器（VCO）的自适应环路增益控制电路根据工作电压和温度的变化补偿振荡控制电流，并补偿锁相环（PLL）系统的增益，从而确保在 PLL电路。