公开(公告)号：US20100200927A1

公开(公告)日：2010-08-12

申请号：US12369099

申请日：2009-02-11

Applicant: Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

Inventor： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

IPC: H01L27/02 ,  H01L21/762 ,  H01L29/51

CPC classification number: H01L21/7624 ,  H01L21/26506 ,  H01L21/84 ,  H01L27/1203

Abstract: A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.

Abstract translation: 绝缘体上半导体衬底和相关半导体结构以及绝缘体上半导体衬底和相关半导体结构的制造方法提供了一种位于并形成在基底半导体内的多阶射频谐波抑制区域 在绝缘体上半导体衬底内的掩埋介质层与基底半导体衬底的界面下方的位置处的衬底。 多级射频谐波抑制区域可以包括离子注入原子，例如但不限于稀有气体原子，以在对射频设备供电时提供抑制的多阶射频谐波，例如但不限于无线电 位于和形成在半导体结构内的表面半导体层内和之上的高频互补金属氧化物半导体器件（或替代地，无源器件）。

公开(公告)号：US07247924B2

公开(公告)日：2007-07-24

申请号：US10695336

申请日：2003-10-28

Applicant: Peter J. Geiss ,  Joseph R. Greco ,  Richard S. Kontra ,  Emily Lanning

Inventor： Peter J. Geiss ,  Joseph R. Greco ,  Richard S. Kontra ,  Emily Lanning

IPC: H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11 ,  H01L21/331 ,  H01L21/8222

CPC classification number: H01L29/6656 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/0804 ,  H01L29/1083 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/66242 ,  H01L29/7375 ,  H01L29/7378 ,  Y10S257/914

Abstract: A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.

Abstract translation: 调制多晶硅层的晶粒尺寸的方法和用该方法制造的器件。 该方法包括在衬底上形成多晶硅层; 并且进行多晶硅粒度调制物质的离子注入到所述多晶硅层中，使得在进行预定退火之后所述注入的多晶硅层的平均所得晶粒尺寸高于或低于平均得到的晶粒尺寸， 在多晶硅层上执行相同的预定退火，而不需要多晶粒度调节物质离子注入。

公开(公告)号：US06939771B2

公开(公告)日：2005-09-06

申请号：US10653925

申请日：2003-09-04

Applicant: Arne W. Ballantine ,  Douglas D. Coolbaugh ,  Jeffrey Gilbert ,  Joseph R. Greco ,  Glenn R. Miller

Inventor： Arne W. Ballantine ,  Douglas D. Coolbaugh ,  Jeffrey Gilbert ,  Joseph R. Greco ,  Glenn R. Miller

IPC: H01L29/73 ,  H01L21/314 ,  H01L21/318 ,  H01L21/328 ,  H01L21/331 ,  H01L29/08

CPC classification number: H01L29/66272 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/0804 ,  H01L29/0895

Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Abstract translation: 一种在半导体材料的两个区域之间形成至少一个界面区域的方法。 在半导体材料的两个区域的至少一部分边界附近形成包含氮的介电材料的至少一个区域，从而控制界面处的电阻。

公开(公告)号：US06703283B1

公开(公告)日：2004-03-09

申请号：US09244958

申请日：1999-02-04

Applicant: Arne W. Ballantine ,  Douglas D. Coolbaugh ,  Jeffrey Gilbert ,  Joseph R. Greco ,  Glenn R. Miller

Inventor： Arne W. Ballantine ,  Douglas D. Coolbaugh ,  Jeffrey Gilbert ,  Joseph R. Greco ,  Glenn R. Miller

IPC: H01L21331

CPC classification number: H01L29/66272 ,  H01L21/3144 ,  H01L21/3185 ,  H01L29/0804 ,  H01L29/0895

Abstract: A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Abstract translation: 一种在半导体材料的两个区域之间形成至少一个界面区域的方法。 在半导体材料的两个区域的至少一部分边界附近形成包含氮的介电材料的至少一个区域，从而控制界面处的电阻。