公开(公告)号：US20100172186A1

公开(公告)日：2010-07-08

申请号：US12724790

申请日：2010-03-16

申请人： June Lee ,  Fred Jaffin, III

发明人： June Lee ,  Fred Jaffin, III

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G06F11/1068 ,  G06F2212/202 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/20 ,  G11C16/26 ,  G11C16/349

摘要： For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells is in response, at least in part, to on a number of program pulses previously required to program the one or more memory cells and/or an erase starting voltage of one or more erase pulses applied to one or more memory cells is based on a number of erase pulses previously required to erase the one or more memory cells. For another embodiment, a program starting voltage level and/or an erase starting voltage level of one or more program and/or erase pulses applied to one or more memory cells is in response, at least in part, to a number of program/erase cycles previously applied to the one or more memory cells.

摘要翻译： 对于一个实施例，施加到一个或多个存储器单元的一个或多个编程脉冲的程序启动电压至少部分地响应于先前需要编程的一个或多个存储器单元和/或 施加到一个或多个存储器单元的一个或多个擦除脉冲的擦除开始电压基于先前需要擦除一个或多个存储单元的擦除脉冲数。 对于另一个实施例，施加到一个或多个存储器单元的一个或多个编程和/或擦除脉冲的程序启动电压电平和/或擦除开始电压电平至少部分地响应于多个编程/擦除 先前施加到一个或多个存储器单元的循环。

公开(公告)号：US20090300311A1

公开(公告)日：2009-12-03

申请号：US12127365

申请日：2008-05-27

申请人： June Lee

发明人： June Lee

IPC分类号： G06F12/00

CPC分类号： G11C7/02 ,  G06F9/30043 ,  G06F9/30109 ,  G06F12/0246 ,  G06F12/0891 ,  G06F2212/214 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C7/1042 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32 ,  G11C2207/2245 ,  G11C2216/14

摘要： The present disclosure includes methods, devices, modules, and systems for storing selective register reset. One method embodiment includes receiving an indication of a die and a plane associated with at least one address cycle. Such a method can also include selectively resetting a particular register of a number of registers, the particular register corresponding to the plane and the die.

摘要翻译： 本公开包括用于存储选择性寄存器复位的方法，设备，模块和系统。 一种方法实施例包括接收与至少一个地址周期相关联的管芯和平面的指示。 这种方法还可以包括选择性地复位多个寄存器的特定寄存器，该特定寄存器对应于该平面和该管芯。

公开(公告)号：US07602644B2

公开(公告)日：2009-10-13

申请号：US11734102

申请日：2007-04-11

申请人： June Lee ,  Oh-Suk Kwon ,  Heung-Soo Im

发明人： June Lee ,  Oh-Suk Kwon ,  Heung-Soo Im

IPC分类号： G11C16/04

CPC分类号： G11C7/1093 ,  G11C7/1006 ,  G11C7/1021 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2207/002 ,  G11C2216/14

摘要： A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.

摘要翻译： 因此，描述了包括具有第一和第二数据寄存器或锁存器的可操作耦合的第一和第二读出放大器的非易失性存储器件和编程方法和装置，用于存储第二放大器的数据的存储电路，用于检查的通过/失败检查电路 第二数据寄存器的内容是存储器件的单元是否已经被充分地编程，以及恢复电路，用于复位第二数据寄存器以重新编程器件直到充分编程。

公开(公告)号：US20070263464A1

公开(公告)日：2007-11-15

申请号：US11382658

申请日：2006-05-10

申请人： Scott Gatzemeier ,  June Lee

发明人： Scott Gatzemeier ,  June Lee

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/26 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/2602

摘要： A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the memory banks. The cache memory is at least as large as the individual memory pages and is used to record the programming voltage required to obtain the specified programming speed as well as the location of defective memory elements. A local on chip state machine may be used to accelerate the programming rate, and there may be a state machine per memory bank. With such an arrangement, the amount of testing time at wafer probe and final packaged device test may be reduced up to 40%, depending upon the number of memory pages tested in parallel.

摘要翻译： 使用位于每个存储体中的高速缓冲存储器来呈现同时测试，轮询和修整不同存储体中的存储器页面的方法。 高速缓冲存储器至少与各个存储器页面一样大，并且用于记录获得指定的编程速度所需的编程电压以及有缺陷的存储器元件的位置。 可以使用本地片上状态机来加速编程速率，并且每个存储体可以存在状态机。 通过这样的布置，根据并行测试的存储器页面的数量，晶片探针和最终封装器件测试的测试时间量可以降低高达40％。

公开(公告)号：US07292487B1

公开(公告)日：2007-11-06

申请号：US11382658

申请日：2006-05-10

申请人： Scott N. Gatzemeier ,  June Lee

发明人： Scott N. Gatzemeier ,  June Lee

IPC分类号： G11C29/00

CPC分类号： G11C29/26 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/2602

摘要： A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the memory banks. The cache memory is at least as large as the individual memory pages and is used to record the programming voltage required to obtain the specified programming speed as well as the location of defective memory elements. A local on chip state machine may be used to accelerate the programming rate, and there may be a state machine per memory bank. With such an arrangement, the amount of testing time at wafer probe and final packaged device test may be reduced up to 40%, depending upon the number of memory pages tested in parallel.

摘要翻译： 使用位于每个存储体中的高速缓冲存储器来呈现同时测试，轮询和修整不同存储体中的存储器页面的方法。 高速缓冲存储器至少与各个存储器页面一样大，并且用于记录获得指定的编程速度所需的编程电压以及有缺陷的存储器元件的位置。 可以使用本地片上状态机来加速编程速率，并且每个存储体可以存在状态机。 通过这样的布置，根据并行测试的存储器页面的数量，晶片探针和最终封装器件测试的测试时间量可以降低高达40％。

公开(公告)号：US07280398B1

公开(公告)日：2007-10-09

申请号：US11514746

申请日：2006-08-31

申请人： June Lee

发明人： June Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C5/02 ,  G11C2216/14

摘要： A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for at least one of the memory planes is initiated during the memory operation for another memory plane. In one embodiment, each of a plurality of programming circuits is associated with a respective memory plane and is operable to program data to the respective memory plane in response to programming signals and when it is enabled. Control logic coupled to the plurality of programming circuits generates programming signals in response to the memory receiving program commands and further generates programming enable signals to individually enable each of the programming circuits to respond to the programming signals and stagger programming of data to each of the memory planes.

摘要翻译： 一种用于在多平面闪存中执行存储器操作的系统和方法。 命令和地址被顺序地提供给存储器以用于存储器平面中的存储器操作。 顺序地启动存储器操作，并且在另一存储器平面的存储器操作期间启动至少一个存储器平面的存储器操作。 在一个实施例中，多个编程电路中的每一个与相应的存储器平面相关联，并且可操作以响应于编程信号将数据编程到相应的存储器平面，并且当其被启用时。 耦合到多个编程电路的控制逻辑响应于存储器接收程序命令而产生编程信号，并进一步产生编程使能信号，以单独使编程电路中的每一个能够对编程信号做出响应，并将数据错开编程到每个存储器 飞机

公开(公告)号：US07221590B2

公开(公告)日：2007-05-22

申请号：US11020900

申请日：2004-12-23

申请人： Jung-Woo Lee ,  June Lee ,  Hyoung-Woo Lee

发明人： Jung-Woo Lee ,  June Lee ,  Hyoung-Woo Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/30

摘要： Flash memory devices are provided including a power supply pad unit. The power supply pad unit includes a first power supply pad, a second power supply pad and a power level detection circuit. The first power and second power supply pads are electrically coupled to the power level detection circuit.

摘要翻译： 提供了包括电源垫单元的闪存设备。 电源焊盘单元包括第一电源焊盘，第二电源焊盘和功率电平检测电路。 第一电源和第二电源焊盘电耦合到功率电平检测电路。

公开(公告)号：US07180811B2

公开(公告)日：2007-02-20

申请号：US10630434

申请日：2003-07-29

申请人： June Lee

发明人： June Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/1063 ,  G11C7/1051 ,  G11C7/24

摘要： A semiconductor memory device has a ready/busy pin for detecting a current state of the device. The memory device includes a voltage level detector, a ready/busy driver controller, and a ready/busy driver. The voltage level detector checks if the internal voltage level has reached a predetermined level, and then generates a power-up signal. The ready/busy driver controller generates a busy enable signal in response to the power-up signal. The ready/busy driver provides the busy enable signal to a ready/busy pin by which it is informed that the memory device is in a busy state.

摘要翻译： 半导体存储器件具有用于检测器件的当前状态的就绪/忙引脚。 存储器件包括电压电平检测器，就绪/忙碌驱动器控制器和就绪/忙碌驱动器。 电压电平检测器检查内部电压电平是否达到预定电平，然后产生上电信号。 准备/繁忙的驱动器控制器响应于上电信号产生忙启动信号。 就绪/忙碌驱动程序将忙碌使能信号提供给就绪/忙碌引脚，通过该引脚通知存储器件处于忙碌状态。

公开(公告)号：US07120056B2

公开(公告)日：2006-10-10

申请号：US10848694

申请日：2004-05-18

申请人： Soon-Young Kim ,  June Lee ,  Oh-Suk Kwon

发明人： Soon-Young Kim ,  June Lee ,  Oh-Suk Kwon

IPC分类号： G11C16/04

CPC分类号： G11C7/1012 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C2207/105

摘要： A flash memory device includes a plurality of data pads to receive data from an adjacent plurality of data pins. A signal generation circuit generates a plurality of selection signals responsive to bit organization and package signals. A buffer circuit buffers the data from the plurality of data pads. An input switch receives the data from the buffer circuit and transmits the data to the data lines responsive to the selection signals. And an output switch provides data to the buffer circuit responsive to the selection signals.

摘要翻译： 闪存器件包括用于从相邻的多个数据引脚接收数据的多个数据焊盘。 信号发生电路响应于位组织和封装信号产生多个选择信号。 缓冲电路缓冲来自多个数据焊盘的数据。 输入开关从缓冲电路接收数据，并响应于选择信号将数据发送到数据线。 并且输出开关响应于选择信号向缓冲器电路提供数据。

公开(公告)号：US20060205212A1

公开(公告)日：2006-09-14

申请号：US11320408

申请日：2005-12-29

申请人： June Lee

发明人： June Lee

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L21/76837 ,  H01L21/76885

摘要： A method for forming a plurality of metal lines in a semiconductor device including forming first insulating layer patterns on a semiconductor substrate, the first insulating patterns being spaced from each other; depositing a metal layer on and between the first insulating layer patterns; planarizing the metal layer; patterning the planarized metal layer to form the plurality of metal lines between the first insulating layer patterns; and forming a second insulating layer on and between the metal lines.