METHOD AND DEVICES FOR TIME AND FREQUENCY SYNCHRONIZATION USING A PHASE LOCKED LOOP
    11.
    发明申请
    METHOD AND DEVICES FOR TIME AND FREQUENCY SYNCHRONIZATION USING A PHASE LOCKED LOOP 有权
    使用相位锁定环路的时间和频率同步的方法和设备

    公开(公告)号:US20150092797A1

    公开(公告)日:2015-04-02

    申请号:US14044075

    申请日:2013-10-02

    Inventor: James Aweya

    CPC classification number: H03L7/1976 H03L2207/50 H04J3/0667 H04J3/0697

    Abstract: This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.

    Abstract translation: 本发明涉及用于时间和频率同步的方法和装置,特别是涉及使用例如IEEE 1588精确时间协议(PTP)的分组网络。 定时协议消息暴露在网络中的伪影,例如分组延迟变化(PDV)或分组丢失。 本发明的实施例提供了一种基于直接数字合成的数字锁相环(DPLL),以提供在从机(时间客户机)上使用的时间和频率信号。 还提供了该DPLL与用于时钟偏移和偏移估计的递归最小二乘机制的示例。

    METHOD AND DEVICES FOR SYNCHRONIZATION
    12.
    发明申请
    METHOD AND DEVICES FOR SYNCHRONIZATION 有权
    用于同步的方法和设备

    公开(公告)号:US20150092793A1

    公开(公告)日:2015-04-02

    申请号:US14043068

    申请日:2013-10-01

    Inventor: James Aweya

    CPC classification number: H04J3/0667 H04J3/0685

    Abstract: This invention relates to methods and devices for time and frequency synchronization. The invention has particular application where time and frequency synchronization over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP) is being carried out. The primary challenge in clock distribution over packet networks is the variable transit delays experienced by timing packets, packet delay variations (PDVs). Embodiments of the invention provide a method for time offset alignment with PDV compensation where a synchronized frequency signal is available at a slave device via Synchronous Ethernet and is used to determine the compensation parameters for the PDV.

    Abstract translation: 本发明涉及用于时间和频率同步的方法和装置。 本发明具有特定的应用,其中使用例如IEEE 1588精确时间协议(PTP)的分组网络进行时间和频率同步。 分组网络中时钟分配的主要挑战是定时分组,分组延迟变化(PDV)所经历的可变传输延迟。 本发明的实施例提供了一种用于与PDV补偿的时间偏移对准的方法,其中同步的频率信号在从属设备经由同步以太网可用并且用于确定PDV的补偿参数。

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