公开(公告)号：US07153087B2

公开(公告)日：2006-12-26

申请号：US10351088

申请日：2003-01-27

申请人： Ki Sang Kang ,  Shuji Akiyama ,  Hiroki Hosaka

发明人： Ki Sang Kang ,  Shuji Akiyama ,  Hiroki Hosaka

IPC分类号： B65G47/24

CPC分类号： H01L21/68 ,  H01L21/67259 ,  H01L21/68735 ,  Y10S414/136 ,  Y10S414/141 ,  Y10T279/26

摘要： A centering unit comprises a plate, centering mechanism, link mechanism, and cylinder mechanism. The plate vertically divides the interior of a frame. The support table is located substantially on the center of the plate. The centering mechanism can center each wafer on the support table. Centering plates of the centering mechanism are located on either side of the support table and have engaging surfaces and that extend along the outer peripheral surface of the wafer. The link mechanism and the cylinder mechanism serve to extend and contract the space between the centering plates.

公开(公告)号：US06642729B2

公开(公告)日：2003-11-04

申请号：US10029031

申请日：2001-12-28

申请人： Ki-sang Kang ,  Sung-mo Kang

发明人： Ki-sang Kang ,  Sung-mo Kang

IPC分类号： G01R3102

CPC分类号： G01R1/07342 ,  Y10S439/912

摘要： A semiconductor integrated circuit wafer tester includes a supporting plate on which a semiconductor wafer may be positioned and a tester head having a circular top plate installed a predetermined distance away from the supporting plate, wherein a probe card in the tester head that includes a circular printed circuit board having a diameter of at least 400 mm (15.75 inches) that is connected to the top plate and having a plurality of probe units formed on the printed circuit board allows electrical parameters of multiple chips formed on the semiconductor wafer to be measured simultaneously.

公开(公告)号：US07838790B2

公开(公告)日：2010-11-23

申请号：US11983635

申请日：2007-11-09

申请人： Seong-goo Kang ,  Jun-ho Lee ,  Ki-sang Kang ,  Hyun-seop Shim ,  Do-young Kam ,  Jae-il Lee ,  Ju-il Kang

发明人： Seong-goo Kang ,  Jun-ho Lee ,  Ki-sang Kang ,  Hyun-seop Shim ,  Do-young Kam ,  Jae-il Lee ,  Ju-il Kang

IPC分类号： B07C5/34

CPC分类号： H01L21/67282 ,  G01R31/2867 ,  G01R31/2893 ,  H01L21/67271 ,  Y10S414/135

摘要： A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.

摘要翻译： 提供了一种用于半导体器件的电测试的多功能处理器系统。 多功能处理器系统包括：（1）半导体器件处理部分，包括包括缓冲器的加载单元，包括单独的标记机的分拣单元和卸载单元; （2）与半导体器件处理部分分离的半导体器件测试部分包括测试室，测试室被分离成两个或更多个测试空间，并且测试室的测试空间包括位于下部的第二室 位置，位于第二室上方的第一室以及用于将第一和第二室彼此连接的管道; 和（3）独立地连接到半导体器件处理部分和半导体器件测试部分并且控制托盘信息，测试结果，标记信息和测试程序信息的主计算机。

公开(公告)号：US20090199059A1

公开(公告)日：2009-08-06

申请号：US12385116

申请日：2009-03-31

申请人： Je-Young Park ,  Ki-Sang Kang

发明人： Je-Young Park ,  Ki-Sang Kang

IPC分类号： G11C29/04 ,  G06F11/22

CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C2029/1806 ,  G11C2029/5606

摘要： A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.

公开(公告)号：US07554349B2

公开(公告)日：2009-06-30

申请号：US11727938

申请日：2007-03-29

申请人： Seong-goo Kang ,  Jun-ho Lee ,  Ki-sang Kang ,  Hyun-seop Shim ,  Do-young Kam ,  Jae-il Lee ,  Ju-il Kang

发明人： Seong-goo Kang ,  Jun-ho Lee ,  Ki-sang Kang ,  Hyun-seop Shim ,  Do-young Kam ,  Jae-il Lee ,  Ju-il Kang

IPC分类号： G01R31/02

CPC分类号： G01R31/2865 ,  G01R31/2862

摘要： A semiconductor device test handler for maintaining stable temperature in a test environment may include a loading unit that loads a plurality of semiconductor devices mounted on a test tray; a soak chamber configured to receive the test tray from the loading unit and to age the semiconductor devices at an aging temperature; and a test chamber configured to receive and test the aged semiconductor devices. The test chamber may include: a test board; a first chamber; a second chamber; one or more pipelines connected to the first and second chambers that allow a temperature-control medium to flow between the first and second chambers; a de-soak chamber that further ages the tested semiconductor devices so that the tested semiconductor devices substantially return to ambient temperature; and a sorting and unloading unit that sorts the tested semiconductor devices according to results of the test and that unloads the sorted semiconductor devices.

摘要翻译： 用于在测试环境中保持稳定温度的半导体器件测试处理器可以包括加载单元，其加载安装在测试托盘上的多个半导体器件; 浸泡室，其构造成从加载单元接收测试托盘并在老化温度下老化半导体器件; 以及被配置为接收和测试老化的半导体器件的测试室。 测试室可以包括：测试板; 第一个房间 第二个房间 连接到第一和第二室的一个或多个管道，允许温度控制介质在第一和第二室之间流动; 脱泡室，其进一步老化测试的半导体器件，使得测试的半导体器件基本上回到环境温度; 以及分类和卸载单元，其根据测试结果对测试的半导体器件进行排序，并且对排序的半导体器件进行卸载。

公开(公告)号：US20050043912A1

公开(公告)日：2005-02-24

申请号：US10851151

申请日：2004-05-24

申请人： Ki-Sang Kang ,  Tsutomu Akiyama ,  Je-Young Park

发明人： Ki-Sang Kang ,  Tsutomu Akiyama ,  Je-Young Park

IPC分类号： G01R31/3183 ,  G01R31/28 ,  G11C29/00 ,  G11C29/56 ,  H01L21/66 ,  G06F19/00

CPC分类号： G11C29/56004 ,  G11C29/56 ,  G11C2029/1208

摘要： Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector, a failure memory, a failure bit counter and a controller for coordinating the operation of the various elements. Depending on the signals received from the controller, the pattern generator will generate background pattern(s) or test patterns and address information that are, in turn, output to the memory device under test and the selector. During funtional testing of the memory device, failure data is accumulated in a failure memory and subsequently output to a failure bit counter using address information from the address pointer while the background or test pattern is being written to the memory device.

摘要翻译： 提供了一种操作这样的装置的存储器件测试装置和方法，其可以减少测试诸如DRAM的存储器件所需的时间。 存储器测试装置包括模式发生器，测试头，地址指针，选择器，故障存储器，故障位计数器和用于协调各种元件的操作的控制器。 根据从控制器接收到的信号，模式发生器将产生背景模式或测试模式和地址信息，这些模式和地址信息又被输出到被测存储器件和选择器。 在对存储器件进行功能测试期间，故障数据被累积在故障存储器中，并且随后当将背景或测试模式写入存储器件时，使用来自地址指针的地址信息将其输出到故障位计数器。

公开(公告)号：US06288955B1

公开(公告)日：2001-09-11

申请号：US09415523

申请日：1999-10-08

申请人： Kazuhiro Shibano ,  Ki-Sang Kang

发明人： Kazuhiro Shibano ,  Ki-Sang Kang

IPC分类号： G11C700

CPC分类号： G01R31/31935 ,  G01R31/31908

摘要： Integrated circuit memory devices are tested by loading into a first defect interpretation memory, results of a preceding comparison test between test pattern data that is input into a memory device and resultant data that is output from the memory device. Automatic switching then takes place to a second defect interpretation memory. The results of a succeeding comparison test are loaded therein, while simultaneously analyzing results from the preceding comparison test in the first defect interpretation memory. Then, automatic switching back to the first defect interpretation memory takes place, and results of a next succeeding comparison test are loaded therein while simultaneously analyzing the results from the succeeding comparison test in the second defect interpretation memory. Automatic switching and automatic switching back are repeatedly performed, to thereby simultaneously test a memory device and analyze memory test results.

摘要翻译： 集成电路存储器件通过加载到第一缺陷解释存储器中进行测试，其中输入到存储器件的测试图案数据与从存储器件输出的结果数据之间的先前的比较测试结果。 然后自动切换到第二个缺陷解释存储器。 在其中加载后续比较测试的结果，同时分析来自第一缺陷解释存储器中的先前比较测试的结果。 然后，自动切换回第一缺陷解释存储器，并且在其中加载下一个后续比较测试的结果，同时分析来自第二缺陷解释存储器中的后续比较测试的结果。 重复执行自动切换和自动切换，从而同时测试存储器件并分析存储器测试结果。

公开(公告)号：US20090206856A1

公开(公告)日：2009-08-20

申请号：US12426719

申请日：2009-04-20

申请人： Jung-Hyun NAM ,  Ki-Sang KANG ,  Gi-Bum KOO ,  Hoon-Jung KIM ,  In-Seok HWANG

发明人： Jung-Hyun NAM ,  Ki-Sang KANG ,  Gi-Bum KOO ,  Hoon-Jung KIM ,  In-Seok HWANG

IPC分类号： G01R31/02

CPC分类号： G01R31/2877

摘要： The present disclosure relates to a wafer burn-in system having a device cooling a probe card and thereby restraining heat accumulation in the probe card. The disclosed wafer burn-in system includes a probe station and a tester. The probe station includes a burn-in chamber, a probe head, and a wafer stage. The probe head has a probe card installed on the lower surface of the probe head. A cooling device restrains heat accumulation in the probe card, e.g., by generating airflow around the probe card. The wafer stage of the burn-in chamber fixes a wafer loaded on the upper surface of the wafer stage and elevates the wafer for contact with the probe card. The tester connects to the probe station through a general purpose interface bus (GPIB) to convey test signals to and from the probe head, and to control operation of the cooling device. The tester activates the cooling device, e.g., activates air blowers to generate airflow forcibly around the probe card and thereby restrain heat accumulation in the probe card during a burn-in process performed in the burn-in chamber.

摘要翻译： 本公开涉及具有冷却探针卡的装置并由此抑制探针卡中的热积聚的晶片老化系统。 所公开的晶片老化系统包括探测台和测试仪。 探针台包括老化室，探针头和晶片台。 探头具有安装在探针头下表面上的探针卡。 冷却装置例如通过在探针卡周围产生气流来限制探针卡中的热积聚。 老化室的晶片台将装载在晶片台的上表面上的晶片固定，并提升晶片以与探针卡接触。 测试仪通过通用接口总线（GPIB）连接到探测站，以将测试信号传送到探头和从探头传出，并控制冷却装置的操作。 测试仪激活冷却装置，例如，激活鼓风机以强制地在探针卡周围产生气流，从而在老化室中进行的老化过程期间抑制探针卡中的热积聚。

公开(公告)号：US20070162794A1

公开(公告)日：2007-07-12

申请号：US11640893

申请日：2006-12-19

申请人： Je-Young Park ,  Ki-Sang Kang

发明人： Je-Young Park ,  Ki-Sang Kang

IPC分类号： G11C29/00

CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C2029/1806 ,  G11C2029/5606

摘要： A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.

摘要翻译： 提供半导体存储器测试装置及其方法。 示例半导体存储器测试设备可以包括被配置为存储被测存储器的至少一个测试结果的故障存储器，模式选择单元，被配置为输出用于选择故障存储器的存储器地址协议的选择信号， 多个测试模式在待测存储器中是有效的，并且地址排列单元被配置为响应于从模式选择单元接收的选择信号而布置地址信号以符合所选择的存储器地址协议。

公开(公告)号：US20060170437A1

公开(公告)日：2006-08-03

申请号：US11330399

申请日：2006-01-12

申请人： Sang-Kyu Yoo ,  Ki-Sang Kang ,  Hoon-Jung Kim ,  Sung-Mo Kang ,  Chang-Hyun Cho

发明人： Sang-Kyu Yoo ,  Ki-Sang Kang ,  Hoon-Jung Kim ,  Sung-Mo Kang ,  Chang-Hyun Cho

IPC分类号： G01R31/02

CPC分类号： G01R1/07364 ,  G01R1/0491

摘要： A probe card for that may be used to test a plurality of semiconductor chips formed on a wafer. The probe card may include a substrate; a plurality of probe blocks that form a pattern corresponding to the pattern formed by the plurality of semiconductor chips formed on the wafer; and a plurality of probe needles formed in the probe blocks and arranged in a pattern corresponding to a plurality of pads formed in the plurality of semiconductor chips. The use of the probe card may decrease the testing time for the wafer.

摘要翻译： 用于其的探针卡可用于测试形成在晶片上的多个半导体芯片。 探针卡可以包括基底; 多个探针块，其形成与由形成在晶片上的多个半导体芯片形成的图案对应的图案; 以及形成在探针块中的多个探针，并以与形成在多个半导体芯片中的多个焊盘相对应的图案布置。 探针卡的使用可能会降低晶片的测试时间。