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    Process for the production of Nb3A1 extra-fine multifilamentary superconducting wire
    11.
    发明授权
    Process for the production of Nb3A1 extra-fine multifilamentary superconducting wire 失效
    生产Nb3A1超细多丝超导线的工艺

    公开(公告)号：US06508889B2

    公开(公告)日：2003-01-21

    申请号：US09826826

    申请日：2001-04-06

    Applicant: Akihiro Kikuchi ,  Yasuo Iijima ,  Kiyoshi Inoue

    Inventor： Akihiro Kikuchi ,  Yasuo Iijima ,  Kiyoshi Inoue

    IPC: H01B1200

    CPC classification number: B21C37/04 ,  B32B15/017 ,  C22C27/02 ,  C22F1/18 ,  H01L39/2409 ,  Y10S420/901 ,  Y10S505/806 ,  Y10S505/815 ,  Y10T29/49014

    Abstract: A high-performance Nb3Al extra-fine multifilamentary superconducting wire is produced simply and inexpensively through the improvement of critical values, Tc, Hc2 and Jc, without the addition of third elements such as Ge, Si and Cu. A first rapid heating and quenching treatment is applied to an Nb/Al composite wire having an atomic ratio of Al to Nb from 1:2.5 to 1:3.5 and having an extra-fine multifilamentary structure to form a BCC alloy phase comprising Nb with Al supersaturatedly dissolved therein wherein the treatment comprises heating the composite wire up to a temperature not lower than 1900° C. within two seconds and then introducing it into a molten metal at a temperature not higher than 400° C. to rapidly quench it. The wire is subjected to a second rapid heating and quenching treatment to form an A15-Nb3Al compound having a low degree of crystalline order but having an approximately stoichiometric composition wherein the second treatment comprises heating the wire up to a temperature not lower than 1500° C. within two seconds and then introducing it into a molten metal at a temperature not higher than 400° C. Then, an additional heat treatment is conducted to improve the degree of crystalline order of the Al5-Nb3Al compound having an approximately stoichiometric composition.

    Abstract translation: 通过提高临界值Tc，Hc2和Jc，不需要添加诸如Ge，Si和Cu的第三元素，简单且廉价地制造高性能Nb3Al超细多丝超导线。 对原子比为Al:Nb的Nb / Al复合线进行第一快速加热淬火处理，其比例为1:2.5〜1:3.5，并且具有超细多丝结构，以形成含有Nb的BCC合金相，Al 过饱和溶解在其中，其中处理包括在两秒钟内将复合线材加热至不低于1900℃的温度，然后在不高于400℃的温度下将其引入熔融金属中以快速淬火。 对线材进行第二次快速加热淬火处理以形成具有低结晶度但具有近似化学计量组成的A15-Nb3Al化合物，其中第二处理包括将线材加热至不低于1500℃的温度 然后在不高于400℃的温度下将其引入熔融金属中，然后进行额外的热处理，以提高具有大致化学计量组成的Al5-Nb3Al化合物的结晶度。

    Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory
    13.
    发明授权
    Storage device with an error correction unit and an improved arrangement for accessing and transferring blocks of data stored in a non-volatile semiconductor memory 有权
    具有错误校正单元的存储设备和用于访问和传送存储在非易失性半导体存储器中的数据块的改进布置

    公开(公告)号：US06317371B2

    公开(公告)日：2001-11-13

    申请号：US09824778

    申请日：2001-04-04

    Applicant: Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

    Inventor： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

    IPC: G11C700

    CPC classification number: G11C16/349 ,  G11C29/76 ,  G11C29/88

    Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

    Abstract translation: 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

    Semiconductor memory device having faulty cells
    14.
    发明授权
    Semiconductor memory device having faulty cells 有权
    具有故障单元的半导体存储器件

    公开(公告)号：US06236601B1

    公开(公告)日：2001-05-22

    申请号：US09477665

    申请日：2000-01-05

    Applicant: Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

    Inventor： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

    IPC: G11C700

    CPC classification number: G11C16/349 ,  G11C29/76 ,  G11C29/88

    Abstract: A semiconductor memory device having an electrically erasable nonvolatile memory, wherein the nonvolatile memory has management information regions for individual blocks and fault registration regions for registering fault addresses. If a block is accessed and found to be faulty, the fault registration is performed so that a partially faulty memory can be used without an increase in access time. By registering the management information address for executing the interchanges of blocks in one-to-one correspondence in the administrative information region, moreover, the blocks can be interchanged depending upon the frequency of rewriting.

    Abstract translation: 一种具有电可擦除非易失性存储器的半导体存储器件，其中非易失性存储器具有用于各个块的管理信息区域和用于登记故障地址的故障登记区域。 如果一个块被访问并发现有故障，则执行故障登记，以便可以使用部分故障的存储器而不增加访问时间。 此外，通过在管理信息区域中一一对应地登记用于执行块的交换的管理信息地址，并且可以根据重写的频率来交换块。

    Information processing system and information processing method for executing instructions in parallel
    15.
    发明授权
    Information processing system and information processing method for executing instructions in parallel 失效
    用于并行执行指令的信息处理系统和信息处理方法

    公开(公告)号：US5671382A

    公开(公告)日：1997-09-23

    申请号：US915204

    申请日：1992-04-20

    Applicant: Yooichi Shintani ,  Kazunori Kuriyama ,  Tohru Shonai ,  Eiki Kamada ,  Kiyoshi Inoue

    Inventor： Yooichi Shintani ,  Kazunori Kuriyama ,  Tohru Shonai ,  Eiki Kamada ,  Kiyoshi Inoue

    IPC: G06F9/38

    CPC classification number: G06F9/3889 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3885

    Abstract: An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.

    Abstract translation: 一种信息处理设备，其中概念地逐个处理指令，并且其结果在概念上有序地写入存储器包括能够并行地解码M个指令和读取操作数的指令控制电路，N（N> / = M）个执行电路能够 执行并行执行多个指令的检测电路，用于确定由指令控制电路解码的M个指令所需的N个执行电路的所有M个执行电路是否为空的检测电路，以及用于保留执行的备用电路 的M解码指令，而检测不能检测到足够的空位。

    Method of producing Cu - Ag alloy based conductive material
    17.
    发明授权
    Method of producing Cu - Ag alloy based conductive material 失效
    生产Cu-Ag合金导电材料的方法

    公开(公告)号：US5534087A

    公开(公告)日：1996-07-09

    申请号：US121379

    申请日：1993-09-15

    Applicant: Tooru Hirota ,  Akira Imai ,  Tomoyuki Kumano ,  Masamitsu Ichihara ,  Yoshikazu Sakai ,  Kiyoshi Inoue ,  Hiroshi Maeda

    Inventor： Tooru Hirota ,  Akira Imai ,  Tomoyuki Kumano ,  Masamitsu Ichihara ,  Yoshikazu Sakai ,  Kiyoshi Inoue ,  Hiroshi Maeda

    IPC: C22C9/00 ,  C22F1/08

    CPC classification number: C22C9/00 ,  C22F1/08

    Abstract: A method for producing a Cu--Ag alloy based conductive material containing about 10% to about 20% at % Ag, that involves the steps of continuously casting the alloy into a rod followed by quickly cooling the rod, cold-working the rod to a reduction in area of 80% or more, then heat treating the cold-worked rod at a temperature of 250.degree. C. to 350.degree. C. for 1 hour or more to form a heat-treated rod, and thereafter cold-working the heat-treated rod to a reduction in area of 90% or more as defined based on the cast rod to produce conductive material having a high strength of 700 MPa or more and conductivity of 75% IACA or more.

    Abstract translation: 一种制备含有约10％至约20％at％Ag的Cu-Ag合金基导电材料的方法，其包括将合金连续铸入棒中的步骤，然后快速冷却棒，将棒冷却至 面积减少80％以上，然后在250〜350℃的温度下对冷加工棒进行1小时以上的热处理，形成热处理棒，然后冷热 根据铸棒测定的面积减小到90％以上的面积，制成具有700MPa以上的高强度和75％IACA以上的导电性的导电材料。

    Semiconductor memory device
    18.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5528535A

    公开(公告)日：1996-06-18

    申请号：US399511

    申请日：1995-03-07

    Applicant: Shigeru Honjo ,  Kazumasa Yanagisawa ,  Kiyoshi Inoue

    Inventor： Shigeru Honjo ,  Kazumasa Yanagisawa ,  Kiyoshi Inoue

    IPC: G11C14/00 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  G11C11/406

    CPC classification number: G11C11/22

    Abstract: A memory matrix--which comprises memory cells arranged in matrix, each made up of a ferroelectric capacitor and an address selection MOSFET--is divided for each word line into a plurality of memory blocks. Each of the memory blocks is provided with a mode storage circuit that stores a DRAM mode (volatile mode) or NV mode (non-volatile mode) in one-to-one correspondence for each memory block, and with a refresh operation count circuit that counts for each memory block the number of times the refresh operations is performed consecutively. During an n-th refresh operation (where n is a predetermined number of times), a memory access is made to temporarily change the plate voltage of the ferroelectric capacitor from one voltage to another and at the same time the mode storage circuit is changed from the DRAM mode to the NV mode. When a read or write operation to and from a memory cell in the memory block is performed, the mode storage circuit is changed from the NV mode to the DRAM mode. The refresh operation is omitted for the memory block that was set to the NV mode according to the stored information in the mode storage circuit.

    Abstract translation: 存储矩阵，其包括以矩阵排列的每个由铁电电容器和地址选择MOSFET构成的存储单元，其被划分为多个存储块。 每个存储块设置有模式存储电路，其针对每个存储块以一对应的对应关系存储DRAM模式（易失性模式）或NV模式（非易失性模式），并且利用刷新操作计数电路 对每个内存块进行连续执行刷新操作的次数。 在第n次刷新操作（其中n是预定次数）的情况下，进行存储器访问以将铁电电容器的板电压从一个电压临时地改变为另一个电压，同时模式存储电路从 DRAM模式为NV模式。 当执行对存储器块中的存储单元的读取或写入操作时，模式存储电路从NV模式改变为DRAM模式。 根据模式存储电路中存储的信息，对于被设置为NV模式的存储器块，省略刷新操作。

    Voltage setting apparatus in a multiplex transmission system
    19.
    发明授权
    Voltage setting apparatus in a multiplex transmission system 失效
    多路传输系统中的电压设定装置

    公开(公告)号：US5404498A

    公开(公告)日：1995-04-04

    申请号：US917059

    申请日：1992-09-15

    Applicant: Motoharu Tanaka ,  Kyosuke Hashimoto ,  Kiyoshi Inoue

    Inventor： Motoharu Tanaka ,  Kyosuke Hashimoto ,  Kiyoshi Inoue

    IPC: H04L12/40 ,  G06F11/00

    CPC classification number: H04L12/40006 ,  H04L2012/40215

    Abstract: Multiplex nodes (11, 12) connected via multiplex transmission lines (A, B and C), a voltage setting unit 16, which changes the voltage of the multiplex transmission line C to a specified value, a controller IC 14, which detects a failure in the multiplex transmission lines A and B, a protective circuit 15, which writes specified address data received from the controller IC 14 and key word data and sends a state signal corresponding to these pieces of data to the voltage setting unit 16, and a controller IC 14 which writes these pieces of data in a predetermined area of the protective circuit 15 are provided. The controller IC 14 detects a failure, the voltage setting unit 16 connects the specified multiplex transmission line C to a power supply or ground according to a state signal received from the protective circuit 15, thus changing the states of the multiplex transmission lines A and B.

    Abstract translation: PCT No.PCT / JP91 / 01686 Sec。 371日期：1992年9月15日 102（e）日期1992年7月30日PCT 1991年12月3日PCT PCT。 公开号WO92 / 10897 日期：1992年6月25日。经由复用传输线（A，B和C）连接的多路复用节点（11,12），将多路复用传输线C的电压改变为指定值的电压设定单元16，控制器 检测多路复用传输线A和B中的故障的IC14，写入从控制器IC 14接收的指定地址数据和关键字数据的保护电路15，并将与这些数据相对应的状态信号发送到电压 设置单元16和将这些数据写入保护电路15的预定区域中的控制器IC 14。 控制器IC14检测到故障，电压设定单元16根据从保护电路15接收的状态信号将指定的多路复用传输线C连接到电源或接地，从而改变多路复用传输线A和B的状态 。

    Data storing system for a communication control circuit
    20.
    发明授权
    Data storing system for a communication control circuit 失效
    用于通信控制电路的数据存储系统

    公开(公告)号：US5311510A

    公开(公告)日：1994-05-10

    申请号：US919911

    申请日：1992-07-27

    Applicant: Hiroo Moriue ,  Yutaka Matsuda ,  Kiyoshi Inoue ,  Yoshikazu Nobutoki ,  Seiji Hirano ,  Hiroaki Sakamoto

    Inventor： Hiroo Moriue ,  Yutaka Matsuda ,  Kiyoshi Inoue ,  Yoshikazu Nobutoki ,  Seiji Hirano ,  Hiroaki Sakamoto

    IPC: G06F13/38 ,  H04L12/56

    CPC classification number: G06F13/385

    Abstract: The data storing system according to the present invention is used for a communication control circuit. The communication control circuit is equipped with a communication sequencer, which takes in a message to be transmitted to a multiplex bus, an ID table which registers data IDs of messages necessary for the station, and the first and second memory circuits which have memory areas keyed to the data IDs. When the communication sequencer takes in a message, it determines whether its data ID exists in the ID table. If the data ID exists and the frequency of occurrence is high, then data following the data ID is temporarily stored in a memory area keyed to a data ID of the first memory circuit. If the data ID exists and the frequency of occurrence is low, then the data following the data ID is temporarily stored in a memory area of the second memory circuit. When a CPU reads the aforementioned stored data, it sets the status area of the storage area, in which the data was stored, for a state that enables a data storage change.

    Abstract translation: 根据本发明的数据存储系统用于通信控制电路。 通信控制电路配备有通信定序器，其接收要发送到多路复用总线的消息，登记该站所需消息的数据ID的ID表以及具有存储区域的第一和第二存储器电路 到数据ID。 当通信定序器接收消息时，它确定其数据ID是否存在于ID表中。 如果数据ID存在且发生频率高，则数据ID之后的数据被临时存储在与第一存储器电路的数据ID相对应的存储区域中。 如果数据ID存在且发生频率低，则数据ID之后的数据被临时存储在第二存储器电路的存储区域中。 当CPU读取上述存储的数据时，它设置存储数据的存储区域的状态区域，以使数据存储改变的状态。

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