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11.发明申请Circuits And Methods For Dual Redundant Register Files With Error Detection And Correction Mechanisms 有权具有错误检测和校正机制的双冗余寄存器文件的电路和方法公开(公告)号：US20100269022A1
公开(公告)日：2010-10-21
申请号：US12626488
申请日：2009-11-25
CPC分类号： G06F11/183 , G06F9/3867 , G06F11/1008 , G06F11/1407 , G06F11/1629 , G06F12/0802 , G06F12/1027
摘要： Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.
摘要翻译： 本文描述了具有错误检测和校正机制的双重冗余寄存器文件的电路和方法的实施例。 本文还描述了其它实施例和相关示例。
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12.发明申请公开(公告)号：US20100269018A1
公开(公告)日：2010-10-21
申请号：US12626479
申请日：2009-11-25
申请人： Lawrence T. Clark , Dan W. Patterson , Xiaoyin Yao
发明人： Lawrence T. Clark , Dan W. Patterson , Xiaoyin Yao
CPC分类号： G06F11/183 , G06F9/3867 , G06F11/1008 , G06F11/1407 , G06F11/1629 , G06F12/0802 , G06F12/1027
摘要： Embodiments of circuits and methods for circuits for the detection of soft errors in cache memories are described herein. Other embodiments and related methods and examples are also described herein.
摘要翻译： 本文描述了用于检测高速缓冲存储器中的软错误的电路的电路和方法的实施例。 本文还描述了其它实施例和相关方法和示例。
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公开(公告)号：US07805625B1
公开(公告)日：2010-09-28
申请号：US12284524
申请日：2008-09-23
申请人： Lawrence T. Clark
发明人： Lawrence T. Clark
IPC分类号： G06F1/30
CPC分类号： H04B1/1615 , H04W52/028 , Y02D70/40
摘要： A method includes providing power to on-die combinatorial circuitry of an integrated circuit (IC) from an external power supply regulator during an active mode of the IC. A state of the on-die combinatorial circuitry of the IC is moved into on-die storage of the IC. Power to the on-die combinational circuitry is disabled during a low power mode of the IC by disrupting power supplied from the external power supply regulator to the IC. A power feedback signal from an internal portion of the IC is provided to the external power supply regulator.
摘要翻译： 一种方法包括在IC的有源模式期间从外部电源调节器向集成电路（IC）的片上组合电路供电。 IC的片上组合电路的状态被移动到IC的片上存储器中。 通过中断从外部电源调节器提供给IC的电源，在IC的低功耗模式下禁止对芯片组合电路的电源。 来自IC内部的功率反馈信号被提供给外部电源调节器。
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公开(公告)号：US07541832B1
公开(公告)日：2009-06-02
申请号：US11742060
申请日：2007-04-30
申请人： Lawrence T. Clark , Giby Samson
发明人： Lawrence T. Clark , Giby Samson
IPC分类号： H03K19/177
CPC分类号： H03K19/1772
摘要： The present invention provides a PLA architecture where the AND plane is implemented with NAND logic. The OR plane may be implemented with various logic, but in one embodiment, the OR plane is implemented with NOR logic. The AND plane may have multiple sequential stages providing hierarchical NAND logic. The NAND logic may be broken into a hierarchy of NAND logic blocks. Each NAND logic block may include one or more series-connected NAND transistor stacks. Each transistor in the transistor stack may receive an input signal representing the product of a PLA clock signal and either a direct PLA input or the complement thereof. As such, the PLA clock is inherently integrated with the input signals that drive the various transistors of the NAND transistor stacks.
摘要翻译： 本发明提供了一种PLA架构，其中AND平面用NAND逻辑实现。 OR平面可以用各种逻辑来实现，但是在一个实施例中，OR平面用NOR逻辑实现。 AND平面可以具有提供分级NAND逻辑的多个连续级。 NAND逻辑可以被分解成NAND逻辑块的层级。 每个NAND逻辑块可以包括一个或多个串联连接的NAND晶体管堆叠。 晶体管堆叠中的每个晶体管可以接收表示PLA时钟信号和直接PLA输入或其互补的乘积的输入信号。 因此，PLA时钟固有地与驱动NAND晶体管堆叠的各种晶体管的输入信号集成。
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15.发明授权Apparatus having a first circuit supplying a power potential to a second circuit under a first operating mode otherwise decoupling the power potential 失效具有第一电路的设备，其在第一操作模式下向第二电路提供功率电势，否则去耦电源电位公开(公告)号：US07010706B2
公开(公告)日：2006-03-07
申请号：US09834408
申请日：2001-04-13
IPC分类号： G06F1/26
摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator that is used to provide a power supply potential to a memory circuit while a logic circuit is decoupled from a power supply potential.
摘要翻译： 简而言之，根据本发明的一个实施例，集成电路具有电压调节器，其用于在逻辑电路与电源电位分离的同时向存储器电路提供电源电位。
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16.发明授权Method and apparatus for employing a light shield to modulate pixel color responsivity 有权采用遮光罩调制像素颜色响应度的方法和装置公开(公告)号：US06933168B2
公开(公告)日：2005-08-23
申请号：US09802464
申请日：2001-03-09
CPC分类号： H01L27/14636 , H01L27/14621 , H01L27/14623 , H01L27/14645 , H01L27/14654 , H01L27/14685 , H01L27/1469
摘要： A method and apparatus for employing a light shield to modulate pixel color responsivity. The improved pixel includes a substrate having a photodiode with a light receiving area. A color filter array material of a first color is disposed above the substrate. The pixel has a first relative responsivity. A light shield is disposed above the substrate to modulate the pixel color responsivity. The light shield forms an aperture whose area is substantially equal to the light receiving area adjusted by a reduction factor. The reduction factor is the result of an arithmetic operation between the first relative responsivity and a second relative responsivity, associated with a second pixel of a second color.
摘要翻译： 一种采用遮光罩来调制像素颜色响应度的方法和装置。 改进的像素包括具有光接收面积的光电二极管的基板。 第一颜色的滤色器阵列材料设置在基板上方。 像素具有第一相对响应度。 遮光板设置在基板上方以调制像素颜色响应度。 遮光板形成其面积基本上等于由减小因子调节的光接收面积的孔径。 缩小因子是与第二颜色的第二像素相关联的第一相对响应度和第二相对响应度之间的算术运算的结果。
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公开(公告)号：US06909651B2
公开(公告)日：2005-06-21
申请号：US10803408
申请日：2004-03-17
申请人： Lawrence T. Clark , Jay B. Miller
发明人： Lawrence T. Clark , Jay B. Miller
摘要： In one embodiment, an array of content addressable memory (CAM) cells include a first plurality of CAM cells and a second plurality of CAM cells. The second plurality of CAM cells has a width sufficient to address a height of the array. A first plurality of CAM drivers are coupled to the array to drive the first plurality of CAM cells. The first plurality of CAM drivers prevent the first plurality of CAM cells from participating in a match when the array is in a test mode.
摘要翻译： 在一个实施例中，内容可寻址存储器（CAM）单元的阵列包括第一多个CAM单元和第二多个CAM单元。 第二组多个CAM单元具有足以解决阵列高度的宽度。 第一多个CAM驱动器耦合到阵列以驱动第一多个CAM单元。 当阵列处于测试模式时，第一组多个CAM驱动程序防止第一多个CAM单元参与匹配。
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公开(公告)号：US06867956B2
公开(公告)日：2005-03-15
申请号：US09746675
申请日：2000-12-22
CPC分类号： H01L27/0266
摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit comprises a charge protection device that is reverse body biased when the integrated circuit is in normal operation.
摘要翻译： 简而言之，根据本发明的一个实施例，集成电路包括电荷保护装置，当集成电路处于正常操作时，该电荷保护装置被反向偏置。
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公开(公告)号：US06744655B2
公开(公告)日：2004-06-01
申请号：US10261395
申请日：2002-09-30
申请人： Lawrence T. Clark , Jay B. Miller
发明人： Lawrence T. Clark , Jay B. Miller
IPC分类号： G11C1500
摘要： In one embodiment, an array of content addressable memory (CAM) cells include a first plurality of CAM cells and a second plurality of CAM cells. The second plurality of CAM cells has a width sufficient to address a height of the array. A first plurality of CAM drivers are coupled to the array to drive the first plurality of CAM cells. The first plurality of CAM drivers prevent the first plurality of CAM cells from participating in a match when the array is in a test mode.
摘要翻译： 在一个实施例中，内容可寻址存储器（CAM）单元的阵列包括第一多个CAM单元和第二多个CAM单元。 第二组多个CAM单元具有足以解决阵列高度的宽度。 第一多个CAM驱动器耦合到阵列以驱动第一多个CAM单元。 当阵列处于测试模式时，第一组多个CAM驱动程序防止第一多个CAM单元参与匹配。
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公开(公告)号：US06707753B2
公开(公告)日：2004-03-16
申请号：US10106975
申请日：2002-03-25
IPC分类号： G11C700
CPC分类号： G11C8/10
摘要： An integrated circuit having CMOS domino logic arranged in multistages or a tree structure. The multistage cells and addressing structure may have applications in a decoder and reduce the number of cells being precharged and reduce the operating power.
摘要翻译： 具有以多级或树结构布置的CMOS多米诺逻辑的集成电路。 多级单元和寻址结构可以在解码器中应用，并且减少预充电的单元的数量并降低操作功率。
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