公开(公告)号：US07952137B2

公开(公告)日：2011-05-31

申请号：US12477121

申请日：2009-06-02

Applicant: Wei-Chieh Lin ,  Li-Cheng Lin

Inventor： Wei-Chieh Lin ,  Li-Cheng Lin

IPC: H01L23/60

CPC classification number: H01L29/7813 ,  H01L27/0255 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/866

Abstract: A trench semiconductor device and a method of making the same are provided. The trench semiconductor device includes a trench MOS device and a trench ESD protection device. The trench ESD protection device is electrically connected between the gate electrode and source electrode of the trench MOS device so as to provide ESD protection. The fabrication of the ESD protection device is integrated into the process of the trench MOS device, and therefore no extra mask is required to define the doped regions of the trench ESD protection device. Consequently, the trench semiconductor device is advantageous for its simplified manufacturing process and low cost.

Abstract translation: 提供了沟槽半导体器件及其制造方法。 沟槽半导体器件包括沟槽MOS器件和沟槽ESD保护器件。 沟槽ESD保护器件电连接在沟槽MOS器件的栅电极和源电极之间，以提供ESD保护。 ESD保护器件的制造集成到沟槽MOS器件的工艺中，因此不需要额外的掩模来限定沟槽ESD保护器件的掺杂区域。 因此，沟槽半导体器件有利于其简化的制造工艺和低成本。

公开(公告)号：US07851310B2

公开(公告)日：2010-12-14

申请号：US12483237

申请日：2009-06-11

Applicant: Li-Cheng Lin ,  Wei-Chieh Lin

Inventor： Li-Cheng Lin ,  Wei-Chieh Lin

IPC: H01L21/338

CPC classification number: H01L29/4236 ,  H01L29/66621 ,  H01L29/78

Abstract: A method for forming semiconductor device, which simultaneously forms a trench MOS transistor device, and an embedded schottky barrier diode (SBD) device in a semiconductor substrate. The embedded SBD device has lower forward voltage drop, which reduces power dissipation. In addition, the voltage bearing ability may be modified easily by virtue of altering the dopant concentration or the width of the voltage bearing dopant region, or the thickness of epitaxial silicon layer. Furthermore, extra cost of purchasing SBD diode may be saved.

Abstract translation: 一种在半导体衬底中同时形成沟槽MOS晶体管器件和嵌入肖特基势垒二极管（SBD）器件的半导体器件的形成方法。 嵌入式SBD器件具有较低的正向压降，从而降低功耗。 此外，由于改变掺杂剂掺杂剂区域的掺杂剂浓度或宽度，或外延硅层的厚度，可以容易地改变电压承载能力。 此外，可以节省购买SBD二极管的额外成本。

公开(公告)号：US20100216290A1

公开(公告)日：2010-08-26

申请号：US12483237

申请日：2009-06-11

Applicant: Li-Cheng Lin ,  Wei-Chieh Lin

Inventor： Li-Cheng Lin ,  Wei-Chieh Lin

IPC: H01L21/336

CPC classification number: H01L29/4236 ,  H01L29/66621 ,  H01L29/78

Abstract: A method for forming semiconductor device, which simultaneously forms a trench MOS transistor device, and an embedded schottky barrier diode (SBD) device in a semiconductor substrate. The embedded SBD device has lower forward voltage drop, which reduces power dissipation. In addition, the voltage bearing ability may be modified easily by virtue of altering the dopant concentration or the width of the voltage bearing dopant region, or the thickness of epitaxial silicon layer. Furthermore, extra cost of purchasing SBD diode may be saved.

公开(公告)号：US20090113086A1

公开(公告)日：2009-04-30

申请号：US12289418

申请日：2008-10-28

Applicant: Chunli Wu ,  Tsung-Liang Lu ,  Chung-Shan Wang ,  Yen-Chen Chen ,  Li-Cheng Lin

Inventor： Chunli Wu ,  Tsung-Liang Lu ,  Chung-Shan Wang ,  Yen-Chen Chen ,  Li-Cheng Lin

IPC: G06F13/00

CPC classification number: H04W72/1284 ,  H04W72/1242

Abstract: A method for providing a buffer status report in a mobile communication network is implemented between a base station and a user equipment. When data arrives to buffers of the user equipment and the priority of a logical channel for the data is higher than those of other logical channels for existing data in the buffers, a short buffer status report associated with the buffer of a logical channel group corresponding to the arrival data is triggered. The user equipment is based on obtained resources allocated by the base station to fill all data of the buffer of the logical channel group in a Protocol Data Unit. If all data of the buffer of the logical channel group corresponding to the arrival data can be completely filled in the Protocol Data Unit, the short buffer status report is canceled. Otherwise, the user equipment transmits the short buffer status report.

Abstract translation: 在基站和用户设备之间实现用于在移动通信网络中提供缓冲器状态报告的方法。 当数据到达用户设备的缓冲器并且用于数据的逻辑信道的优先级高于用于缓冲器中的现有数据的其他逻辑信道的优先级时，与缓冲器中的对应于逻辑信道组的缓冲器相关联的短缓冲状态报告 到达数据被触发。 用户设备基于由基站分配的获得的资源来填充协议数据单元中的逻辑信道组的缓冲器的所有数据。 如果对应于到达数据的逻辑信道组的缓冲器的所有数据都可以完全填充到协议数据单元中，则缓冲器状态报告被取消。 否则，用户设备发送短暂缓冲状态报告。

公开(公告)号：US08241978B2

公开(公告)日：2012-08-14

申请号：US12536504

申请日：2009-08-06

Applicant: Wei-Chieh Lin ,  Li-Cheng Lin ,  Hsin-Yu Hsu ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Chia-Hui Chen ,  Shih-Chieh Hung

Inventor： Wei-Chieh Lin ,  Li-Cheng Lin ,  Hsin-Yu Hsu ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Chia-Hui Chen ,  Shih-Chieh Hung

IPC: H01L27/06 ,  H01L21/336

CPC classification number: H01L27/0629 ,  H01L29/8725

Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.

Abstract translation: 具有集成MOSFET和肖特基二极管的半导体器件包括其上限定有MOSFET区和肖特基二极管区的衬底; 形成在所述MOSFET区域中的多个第一沟槽; 以及形成在肖特基二极管区域中的多个第二沟槽。 分别包括形成在第一沟槽的侧壁和底部上的第一绝缘层的第一沟槽和填充第一沟槽的第一导电层用作沟槽MOSFET的沟槽栅极。 第二沟槽分别包括形成在第二沟槽的侧壁和底部上的第二绝缘层和填充第二沟槽的第二导电层。 第二沟槽的深度和宽度大于第一沟槽的深度和宽度; 并且所述第二绝缘层的厚度大于所述第一绝缘层的厚度。

公开(公告)号：US07203783B2

公开(公告)日：2007-04-10

申请号：US10999981

申请日：2004-12-01

Applicant: Li-Cheng Lin

Inventor： Li-Cheng Lin

IPC: G06F13/00 ,  G06F3/00

CPC classification number: G06F3/0607 ,  G06F3/0661 ,  G06F3/0677

Abstract: An electrical host system includes a host and an expandable optical disk recording and playing device. The expandable optical disk recording and playing device includes an expanding interface module, an expanding interface, a storage interface module, an output interface module and a CODEC module. The expanding interface module connects to the expanding interface and the host. The storage interface module connects to a storage device. The CODEC module encodes, decodes or transcodes an audio/video source to generate audio/video data, wherein the audio/video source is inputted from the host through the expanding interface and the expanding interface module. The audio/video data are outputted through the output interface module, or through the storage interface module to the storage device.

Abstract translation: 电主机系统包括主机和可扩展光盘记录和播放设备。 可扩展光盘记录和播放装置包括扩展接口模块，扩展接口，存储接口模块，输出接口模块和CODEC模块。 扩展接口模块连接到扩展接口和主机。 存储接口模块连接到存储设备。 CODEC模块对音频/视频源进行编码，解码或转码以产生音频/视频数据，其中通过扩展接口和扩展接口模块从主机输入音频/视频源。 音频/视频数据通过输出接口模块或存储接口模块输出到存储设备。

公开(公告)号：US20050251587A1

公开(公告)日：2005-11-10

申请号：US10998611

申请日：2004-11-30

Applicant: Li-Cheng Lin ,  Benjamin Pan

Inventor： Li-Cheng Lin ,  Benjamin Pan

IPC: G06F13/10 ,  G11B33/00 ,  H04N5/765 ,  H04N5/85

CPC classification number: H04N5/765 ,  H04N5/85

Abstract: An expandable optical disk recording and playing system and main board thereof including an input interface module; a PCI expanding interface module, which includes a PCI bus and an expanding component for connecting to a expanding interface, the expanding interface connecting to an expandable external device; a storage interface module, which is used to connect to a storage device; an output interface module; and a CODEC module, which encodes, decodes or transcodes an audio/video source to generate audio/video data, wherein the audio/video source is inputted from the input interface module, the PCI expanding interface module, or the storage interface module, and the audio/video data is outputted through the output interface module, through the PCI expanding interface module to the external device, or through the storage interface module to the storage device.

Abstract translation: 一种可扩展光盘记录和播放系统及其主板，包括输入接口模块; PCI扩展接口模块，其包括PCI总线和用于连接到扩展接口的扩展组件，扩展接口连接到可扩展外部设备; 存储接口模块，用于连接到存储设备; 输出接口模块; 以及CODEC模块，其对音频/视频源进行编码，解码或转码以产生音频/视频数据，其中音频/视频源从输入接口模块，PCI扩展接口模块或存储接口模块输入，以及 音频/视频数据通过输出接口模块，通过PCI扩展接口模块输出到外部设备，或通过存储接口模块输出到存储设备。

公开(公告)号：US08168480B2

公开(公告)日：2012-05-01

申请号：US12563172

申请日：2009-09-21

Applicant: Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

Inventor： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

IPC: H01L21/332

CPC classification number: H01L29/7395 ,  H01L29/0834 ,  H01L29/66333

Abstract: An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.

Abstract translation: IGBT和二极管的集成结构包括多个掺杂的阴极区域，并且提供其形成方法。 掺杂阴极区域堆叠在半导体衬底中，彼此重叠并接触。 与其他掺杂阴极区域相比，掺杂阴极区域越高，掺杂阴极区域的注入面积越大。 掺杂阴极区域和半导体衬底具有不同的导电类型，并且被施加作为二极管的阴极和IGBT的集电极。 堆叠的掺杂阴极区域可以增加阴极的薄度，并且防止晶片过度变薄和破裂。

公开(公告)号：US20100301386A1

公开(公告)日：2010-12-02

申请号：US12563172

申请日：2009-09-21

Applicant: Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

Inventor： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

IPC: H01L27/06 ,  H01L21/77

CPC classification number: H01L29/7395 ,  H01L29/0834 ,  H01L29/66333

Abstract: An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.

Abstract translation: IGBT和二极管的集成结构包括多个掺杂的阴极区域，并且提供其形成方法。 掺杂阴极区域堆叠在半导体衬底中，彼此重叠并接触。 与其他掺杂阴极区域相比，掺杂阴极区域越高，掺杂阴极区域的注入面积越大。 掺杂阴极区域和半导体衬底具有不同的导电类型，并且被施加作为二极管的阴极和IGBT的集电极。 堆叠的掺杂阴极区域可以增加阴极的薄度，并且防止晶片过度变薄和破裂。

公开(公告)号：US20100258853A1

公开(公告)日：2010-10-14

申请号：US12477121

申请日：2009-06-02

Applicant: Wei-Chieh Lin ,  Li-Cheng Lin

Inventor： Wei-Chieh Lin ,  Li-Cheng Lin

IPC: H01L29/78 ,  H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L27/0255 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/866

Abstract: A trench semiconductor device and a method of making the same are provided. The trench semiconductor device includes a trench MOS device and a trench ESD protection device. The trench ESD protection device is electrically connected between the gate electrode and source electrode of the trench MOS device so as to provide ESD protection. The fabrication of the ESD protection device is integrated into the process of the trench MOS device, and therefore no extra mask is required to define the doped regions of the trench ESD protection device. Consequently, the trench semiconductor device is advantageous for its simplified manufacturing process and low cost.

Abstract translation: 提供了沟槽半导体器件及其制造方法。 沟槽半导体器件包括沟槽MOS器件和沟槽ESD保护器件。 沟槽ESD保护器件电连接在沟槽MOS器件的栅电极和源电极之间，以提供ESD保护。 ESD保护器件的制造集成到沟槽MOS器件的工艺中，因此不需要额外的掩模来限定沟槽ESD保护器件的掺杂区域。 因此，沟槽半导体器件有利于其简化的制造工艺和低成本。