公开(公告)号：US20100289075A1

公开(公告)日：2010-11-18

申请号：US12536504

申请日：2009-08-06

Applicant: Wei-Chieh Lin ,  Li-Cheng Lin ,  Hsin-Yu Hsu ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Chia-Hui Chen ,  Shih-Chieh Hung

Inventor： Wei-Chieh Lin ,  Li-Cheng Lin ,  Hsin-Yu Hsu ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Chia-Hui Chen ,  Shih-Chieh Hung

IPC: H01L27/06 ,  H01L21/8234 ,  H01L21/336

CPC classification number: H01L27/0629 ,  H01L29/8725

Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.

Abstract translation: 具有集成MOSFET和肖特基二极管的半导体器件包括其上限定有MOSFET区和肖特基二极管区的衬底; 形成在所述MOSFET区域中的多个第一沟槽; 以及形成在肖特基二极管区域中的多个第二沟槽。 分别包括形成在第一沟槽的侧壁和底部上的第一绝缘层的第一沟槽和填充第一沟槽的第一导电层用作沟槽MOSFET的沟槽栅极。 第二沟槽分别包括形成在第二沟槽的侧壁和底部上的第二绝缘层和填充第二沟槽的第二导电层。 第二沟槽的深度和宽度大于第一沟槽的深度和宽度; 并且所述第二绝缘层的厚度大于所述第一绝缘层的厚度。

公开(公告)号：US20090175253A1

公开(公告)日：2009-07-09

申请号：US12318636

申请日：2009-01-05

Applicant: Chunli Wu ,  Li-Cheng Lin ,  Chung-Shan Wang ,  Tsung-Liang Lu

Inventor： Chunli Wu ,  Li-Cheng Lin ,  Chung-Shan Wang ,  Tsung-Liang Lu

IPC: H04W4/00

CPC classification number: H04W99/00 ,  H04W74/08

Abstract: A frame format for random access response of wireless communication transmission is provided. The frame format comprises a header segment and a variable length data segment. The header segment includes one or more random access response subheader and 0 to N load control subheader. The variable length data segment including one or more random access response data payload corresponding to the one or more random access response subheader. The one or more random access response subheader includes a status indication field to represent a last random access response subheader, a load control subheader, a random access response data payload with a T-CRNTI field, or a random access response data payload without a T-CRNTI field.

Abstract translation: 提供了一种用于无线通信传输的随机接入响应的帧格式。 帧格式包括标题段和可变长度数据段。 标题段包括一个或多个随机接入响应子报头和0到N个负载控制子报头。 所述可变长度数据段包括与所述一个或多个随机接入响应子报头相对应的一个或多个随机接入响应数据净荷。 一个或多个随机接入响应子报头包括用于表示最后一个随机接入响应子报头的状态指示字段，负载控制子报头，具有T-CRNTI字段的随机接入响应数据有效载荷或者没有T的随机接入响应数据有效载荷 -CRNTI字段。

公开(公告)号：US08241978B2

公开(公告)日：2012-08-14

申请号：US12536504

申请日：2009-08-06

Applicant: Wei-Chieh Lin ,  Li-Cheng Lin ,  Hsin-Yu Hsu ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Chia-Hui Chen ,  Shih-Chieh Hung

Inventor： Wei-Chieh Lin ,  Li-Cheng Lin ,  Hsin-Yu Hsu ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Chia-Hui Chen ,  Shih-Chieh Hung

IPC: H01L27/06 ,  H01L21/336

CPC classification number: H01L27/0629 ,  H01L29/8725

Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.

Abstract translation: 具有集成MOSFET和肖特基二极管的半导体器件包括其上限定有MOSFET区和肖特基二极管区的衬底; 形成在所述MOSFET区域中的多个第一沟槽; 以及形成在肖特基二极管区域中的多个第二沟槽。 分别包括形成在第一沟槽的侧壁和底部上的第一绝缘层的第一沟槽和填充第一沟槽的第一导电层用作沟槽MOSFET的沟槽栅极。 第二沟槽分别包括形成在第二沟槽的侧壁和底部上的第二绝缘层和填充第二沟槽的第二导电层。 第二沟槽的深度和宽度大于第一沟槽的深度和宽度; 并且所述第二绝缘层的厚度大于所述第一绝缘层的厚度。

公开(公告)号：US07203783B2

公开(公告)日：2007-04-10

申请号：US10999981

申请日：2004-12-01

Applicant: Li-Cheng Lin

Inventor： Li-Cheng Lin

IPC: G06F13/00 ,  G06F3/00

CPC classification number: G06F3/0607 ,  G06F3/0661 ,  G06F3/0677

Abstract: An electrical host system includes a host and an expandable optical disk recording and playing device. The expandable optical disk recording and playing device includes an expanding interface module, an expanding interface, a storage interface module, an output interface module and a CODEC module. The expanding interface module connects to the expanding interface and the host. The storage interface module connects to a storage device. The CODEC module encodes, decodes or transcodes an audio/video source to generate audio/video data, wherein the audio/video source is inputted from the host through the expanding interface and the expanding interface module. The audio/video data are outputted through the output interface module, or through the storage interface module to the storage device.

Abstract translation: 电主机系统包括主机和可扩展光盘记录和播放设备。 可扩展光盘记录和播放装置包括扩展接口模块，扩展接口，存储接口模块，输出接口模块和CODEC模块。 扩展接口模块连接到扩展接口和主机。 存储接口模块连接到存储设备。 CODEC模块对音频/视频源进行编码，解码或转码以产生音频/视频数据，其中通过扩展接口和扩展接口模块从主机输入音频/视频源。 音频/视频数据通过输出接口模块或存储接口模块输出到存储设备。

公开(公告)号：US20050251587A1

公开(公告)日：2005-11-10

申请号：US10998611

申请日：2004-11-30

Applicant: Li-Cheng Lin ,  Benjamin Pan

Inventor： Li-Cheng Lin ,  Benjamin Pan

IPC: G06F13/10 ,  G11B33/00 ,  H04N5/765 ,  H04N5/85

CPC classification number: H04N5/765 ,  H04N5/85

Abstract: An expandable optical disk recording and playing system and main board thereof including an input interface module; a PCI expanding interface module, which includes a PCI bus and an expanding component for connecting to a expanding interface, the expanding interface connecting to an expandable external device; a storage interface module, which is used to connect to a storage device; an output interface module; and a CODEC module, which encodes, decodes or transcodes an audio/video source to generate audio/video data, wherein the audio/video source is inputted from the input interface module, the PCI expanding interface module, or the storage interface module, and the audio/video data is outputted through the output interface module, through the PCI expanding interface module to the external device, or through the storage interface module to the storage device.

Abstract translation: 一种可扩展光盘记录和播放系统及其主板，包括输入接口模块; PCI扩展接口模块，其包括PCI总线和用于连接到扩展接口的扩展组件，扩展接口连接到可扩展外部设备; 存储接口模块，用于连接到存储设备; 输出接口模块; 以及CODEC模块，其对音频/视频源进行编码，解码或转码以产生音频/视频数据，其中音频/视频源从输入接口模块，PCI扩展接口模块或存储接口模块输入，以及 音频/视频数据通过输出接口模块，通过PCI扩展接口模块输出到外部设备，或通过存储接口模块输出到存储设备。

公开(公告)号：US08168480B2

公开(公告)日：2012-05-01

申请号：US12563172

申请日：2009-09-21

Applicant: Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

Inventor： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

IPC: H01L21/332

CPC classification number: H01L29/7395 ,  H01L29/0834 ,  H01L29/66333

Abstract: An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.

Abstract translation: IGBT和二极管的集成结构包括多个掺杂的阴极区域，并且提供其形成方法。 掺杂阴极区域堆叠在半导体衬底中，彼此重叠并接触。 与其他掺杂阴极区域相比，掺杂阴极区域越高，掺杂阴极区域的注入面积越大。 掺杂阴极区域和半导体衬底具有不同的导电类型，并且被施加作为二极管的阴极和IGBT的集电极。 堆叠的掺杂阴极区域可以增加阴极的薄度，并且防止晶片过度变薄和破裂。

公开(公告)号：US20100301386A1

公开(公告)日：2010-12-02

申请号：US12563172

申请日：2009-09-21

Applicant: Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

Inventor： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

IPC: H01L27/06 ,  H01L21/77

CPC classification number: H01L29/7395 ,  H01L29/0834 ,  H01L29/66333

Abstract: An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.

Abstract translation: IGBT和二极管的集成结构包括多个掺杂的阴极区域，并且提供其形成方法。 掺杂阴极区域堆叠在半导体衬底中，彼此重叠并接触。 与其他掺杂阴极区域相比，掺杂阴极区域越高，掺杂阴极区域的注入面积越大。 掺杂阴极区域和半导体衬底具有不同的导电类型，并且被施加作为二极管的阴极和IGBT的集电极。 堆叠的掺杂阴极区域可以增加阴极的薄度，并且防止晶片过度变薄和破裂。

公开(公告)号：US20100258853A1

公开(公告)日：2010-10-14

申请号：US12477121

申请日：2009-06-02

Applicant: Wei-Chieh Lin ,  Li-Cheng Lin

Inventor： Wei-Chieh Lin ,  Li-Cheng Lin

IPC: H01L29/78 ,  H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L27/0255 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/866

Abstract: A trench semiconductor device and a method of making the same are provided. The trench semiconductor device includes a trench MOS device and a trench ESD protection device. The trench ESD protection device is electrically connected between the gate electrode and source electrode of the trench MOS device so as to provide ESD protection. The fabrication of the ESD protection device is integrated into the process of the trench MOS device, and therefore no extra mask is required to define the doped regions of the trench ESD protection device. Consequently, the trench semiconductor device is advantageous for its simplified manufacturing process and low cost.

Abstract translation: 提供了沟槽半导体器件及其制造方法。 沟槽半导体器件包括沟槽MOS器件和沟槽ESD保护器件。 沟槽ESD保护器件电连接在沟槽MOS器件的栅电极和源电极之间，以提供ESD保护。 ESD保护器件的制造集成到沟槽MOS器件的工艺中，因此不需要额外的掩模来限定沟槽ESD保护器件的掺杂区域。 因此，沟槽半导体器件有利于其简化的制造工艺和低成本。

公开(公告)号：US20100055857A1

公开(公告)日：2010-03-04

申请号：US12334492

申请日：2008-12-14

Applicant: Wei-Chieh Lin ,  Hsin-Yu Hsu ,  Hsin-Yen Chiu ,  Shih-Chieh Hung ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin

Inventor： Wei-Chieh Lin ,  Hsin-Yu Hsu ,  Hsin-Yen Chiu ,  Shih-Chieh Hung ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66734

Abstract: A method of forming a power device includes providing a substrate, a semiconductor layer having at least a trench and being disposed on the substrate, a gate insulating layer covering the semiconductor layer, and a conductive material disposed in the trench, performing an ion implantation process to from a body layer, performing a tilted ion implantation process to from a heavy doped region, forming a first dielectric layer overall, performing a chemical mechanical polishing process until the body layer disposed under the heavy doped region is exposed to form source regions on the opposite sides of the trench, and forming a source trace directly covering the source regions disposed on the opposite sides of the trench.

Abstract translation: 一种形成功率器件的方法包括提供衬底，至少具有沟槽并设置在衬底上的半导体层，覆盖半导体层的栅极绝缘层和设置在沟槽中的导电材料，执行离子注入工艺 从体层进行倾斜的离子注入工艺，从重掺杂区域进行倾斜的离子注入工艺，整体形成第一介电层，进行化学机械抛光工艺，直到布置在重掺杂区域之下的体层露出，形成源区 并且形成直接覆盖设置在沟槽的相对侧上的源极区域的源极迹线。

公开(公告)号：US08072067B2

公开(公告)日：2011-12-06

申请号：US12436266

申请日：2009-05-06

Applicant: Ming-Chung Chian ,  Tsan-Yao Cheng ,  Li-Cheng Lin ,  Hong-Hsiang Tsai

Inventor： Ming-Chung Chian ,  Tsan-Yao Cheng ,  Li-Cheng Lin ,  Hong-Hsiang Tsai

IPC: H01L23/48

CPC classification number: H01L23/525 ,  H01L23/53223 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/11462 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01044 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15788 ,  H01L2924/3651 ,  H01L2924/01014 ,  H01L2924/04941 ,  H01L2924/01022 ,  H01L2924/00014 ,  H01L2924/0496 ,  H01L2924/0498 ,  H01L2924/0499 ,  H01L2924/0494 ,  H01L2924/04953 ,  H01L2924/00

Abstract: A semiconductor structure including a substrate, an insulating layer, a composite pad structure, a passivation layer, and a bump is provided. A circuit structure is disposed on the substrate. The insulating layer covers the substrate and has a first opening exposing the circuit structure. The composite pad structure includes a first conductive layer, a barrier layer, and a second conductive layer which are sequentially disposed. The composite pad structure is disposed on the insulating layer and fills the first opening to electrically connect to the circuit structure. The passivation layer covers the composite pad structure and has a second opening exposing the composite pad structure. The bump fills the second opening and electrically connects to the composite pad structure.

Abstract translation: 提供了包括衬底，绝缘层，复合衬垫结构，钝化层和凸块的半导体结构。 电路结构设置在基板上。 绝缘层覆盖基板并且具有暴露电路结构的第一开口。 复合焊盘结构包括依次布置的第一导电层，阻挡层和第二导电层。 复合焊盘结构设置在绝缘层上并填充第一开口以电连接到电路结构。 钝化层覆盖复合焊盘结构，并具有露出复合焊盘结构的第二开口。 凸块填充第二开口并电连接到复合垫结构。