公开(公告)号：US06448182B1

公开(公告)日：2002-09-10

申请号：US09447172

申请日：1999-11-22

申请人： Lindsey Hall ,  Jennifer Sees ,  Ashutosh Misra

发明人： Lindsey Hall ,  Jennifer Sees ,  Ashutosh Misra

IPC分类号： H01L21302

CPC分类号： H01L21/3212 ,  B24B37/044 ,  C09K3/1463

摘要： An embodiment of the instant invention is a method of fabricating an electrical device having a structure overlying a semiconductor substrate which is planarized using chemical mechanical planarization, the method comprising the steps of: forming a layer of material over the semiconductor wafer; polishing the layer of material by subjecting it to a polishing pad and a slurry which includes peroxygen; and wherein the slurry additionally includes a stabilizing agent which retards the decomposition of the peroxygen in the slurry. Preferably, the stabilizing agent is comprised of: pyrophosphoric acids, polyphosphonic acids, polyphosphoric acids, Ethylenediamine Tetraacetic acid, a salt of the pyrophosphoric acids, a salt of the polyphosphonic acids, a salt of the polyphosphoric acids, a salt of the Ethylenediamine Tetraacetic acid and any combination thereof. In addition, the stabilizing agent may be comprised of: sodium pyrophosphate decahydrate, sodium pyrophosphate decahydrate, and/or 8-hydroxyquinoline. The decomposition of the peroxygen in the slurry is catalyzed by transition metals included in the slurry, and may be caused by the pH of the slurry. The layer of material is, preferably, comprised of: tungsten, copper, aluminum, a dielectric material, and any combination thereof.

摘要翻译： 本发明的一个实施例是制造具有覆盖半导体衬底的结构的电子器件的方法，其使用化学机械平面化进行平面化，所述方法包括以下步骤：在半导体晶片上形成材料层; 通过使抛光垫和包括过氧化物的浆料进行抛光来抛光材料层; 并且其中所述浆料另外包括阻止所述浆料中过氧化物分解的稳定剂。 优选地，稳定剂包括：焦磷酸，多膦酸，多磷酸，乙二胺四乙酸，焦磷酸盐，多膦酸的盐，多磷酸的盐，乙二胺四乙酸的盐 及其任何组合。 此外，稳定剂可以包括：十水合焦磷酸钠，十水合焦磷酸钠和/或8-羟基喹啉。 浆料中过氧化物的分解由包含在浆料中的过渡金属催化，并且可能由浆料的pH引起。 材料层优选地包括：钨，铜，铝，介电材料及其任何组合。

公开(公告)号：US20130001786A1

公开(公告)日：2013-01-03

申请号：US13171657

申请日：2011-06-29

申请人： Brett H. Engel ,  Lindsey Hall ,  David F. Hilscher ,  Randolph F. Knarr ,  Steven R. Soss ,  Jin Z. Wallner

发明人： Brett H. Engel ,  Lindsey Hall ,  David F. Hilscher ,  Randolph F. Knarr ,  Steven R. Soss ,  Jin Z. Wallner

IPC分类号： H01L21/28 ,  H01L23/48

CPC分类号： H01L23/528 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.

摘要翻译： 在半导体器件中形成重叠触点的方法包括在电介质层中形成第一触点; 蚀刻电介质层以形成与第一接触相邻的凹部，并且在蚀刻介电层的同时去除第一接触的顶部，其中在电介质层中形成凹部之后第一接触的底部保留在电介质层中 ; 以及在与所述第一接触件的底部相邻的所述凹部中形成第二触点，并且在所述第一接触件的底部的顶表面的顶部上形成第二接触。

公开(公告)号：US20070278524A1

公开(公告)日：2007-12-06

申请号：US11772508

申请日：2007-07-02

申请人： Lindsey Hall

发明人： Lindsey Hall

IPC分类号： H01L27/088

CPC分类号： H01L29/165 ,  H01L21/823412 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.

摘要翻译： 一种形成集成电路晶体管（50）的方法。 该方法提供第一半导体区域（52）并且相对于第一半导体区域形成（110）栅极结构（54×x））在固定位置。 栅极结构具有第一侧壁和第二侧壁（59）。 该方法还形成与第一侧壁和第二侧壁相邻的至少第一层（58××，60×x×）。 该方法还在第一半导体区域中形成（120）至少一个凹部（62×x /），并从栅极结构横向向外延伸。 该方法中的附加步骤首先是氧化（130）所述至少一个凹部，使得在其中形成氧化材料，其次，剥离（140）所述氧化材料的至少一部分，以及第三，形成（160）第二 半导体区域（66×x））。

公开(公告)号：US07253086B2

公开(公告)日：2007-08-07

申请号：US10967766

申请日：2004-10-18

申请人： Lindsey Hall

发明人： Lindsey Hall

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/165 ,  H01L21/823412 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.

摘要翻译： 一种形成集成电路晶体管（50）的方法。 该方法提供第一半导体区域（52）并且相对于第一半导体区域形成（110）栅极结构（54×x））在固定位置。 栅极结构具有第一侧壁和第二侧壁（59）。 该方法还形成与第一侧壁和第二侧壁相邻的至少第一层（58××，60×x×）。 该方法还在第一半导体区域中形成（120）至少一个凹部（62×x /），并从栅极结构横向向外延伸。 该方法中的附加步骤首先是氧化（130）所述至少一个凹部，使得在其中形成氧化材料，其次，剥离（140）所述氧化材料的至少一部分，以及第三，形成（160）第二 半导体区域（66×x））。

公开(公告)号：US07217626B2

公开(公告)日：2007-05-15

申请号：US10899360

申请日：2004-07-26

申请人： Haowen Bu ,  PR Chidambaram ,  Rajesh Khamankar ,  Lindsey Hall

发明人： Haowen Bu ,  PR Chidambaram ,  Rajesh Khamankar ,  Lindsey Hall

IPC分类号： H01L21/336

CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of the second sidewall spacer (120b) after implanting the source/drain region (116), where the remaining sidewall spacer (120a) is narrower following the source/drain implant to improve source/drain contact resistance and PMD gap fill, and to facilitate inducing stress in the transistor channel.

摘要翻译： 呈现用于晶体管制造的方法（50），其中第一和第二侧壁间隔物（120a，120b）从栅极结构（114）横向向外形成，之后植入源极/漏极区（116）。 方法（50）还包括在注入源极/漏极区域（116）之后去除第二侧壁间隔物（120b）的全部或一部分，其中剩余侧壁间隔物（120a）在源极/漏极植入物之后更窄 改善源极/漏极接触电阻和PMD间隙填充，并促进晶体管沟道中的应力。

公开(公告)号：US07153706B2

公开(公告)日：2006-12-26

申请号：US10829053

申请日：2004-04-21

申请人： Sanjeev Aggarwal ,  Kelly J. Taylor ,  Lindsey Hall ,  Satyavolu Srinivas Papa Rao

发明人： Sanjeev Aggarwal ,  Kelly J. Taylor ,  Lindsey Hall ,  Satyavolu Srinivas Papa Rao

IPC分类号： H01L21/00

CPC分类号： H01L27/11585 ,  H01L21/31053 ,  H01L27/11502 ,  H01L27/1159 ,  H01L28/55

摘要： The present invention provides a ferroelectric capacitor, a method of manufacture therefor, and a method of manufacturing a ferroelectric random access memory (FeRAM) device. The ferroelectric capacitor (100), among other elements, includes a substantially planar ferroelectric dielectric layer (165) located over a first electrode layer (160), wherein the substantially planar ferroelectric dielectric layer (165) has an average surface roughness of less than about 4 nm. The ferroelectric capacitor (100) further includes a second electrode layer (170) located over the substantially planar ferroelectric dielectric layer (165).

摘要翻译： 本发明提供一种铁电电容器及其制造方法，以及制造铁电随机存取存储器（FeRAM）器件的方法。 除了其他元件之外，铁电电容器（100）包括位于第一电极层（160）上方的基本平坦的铁电介质层（165），其中基本上平坦的铁电介质层（165）的平均表面粗糙度小于约 4nm。 铁电电容器（100）还包括位于基本上平坦的铁电介质层（165）上方的第二电极层（170）。

公开(公告)号：US07060579B2

公开(公告)日：2006-06-13

申请号：US10902360

申请日：2004-07-29

申请人： PR Chidambaram ,  Lindsey Hall ,  Haowen Bu

发明人： PR Chidambaram ,  Lindsey Hall ,  Haowen Bu

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636

摘要： A method (100) of forming a transistor includes forming a gate structure (108) over a semiconductor body and forming recesses (112) using an isotropic etch using the gate structure as an etch mask. The isotropic etch forms a recess in the semiconductor body that extends laterally in the semiconductor body toward a channel portion of the semiconductor body underlying the gate structure. The method further includes epitaxially growing silicon (114) comprising stress-inducing species in the recesses. The source and drain regions are then implanted (120) in the semiconductor body on opposing sides of the gate structure.

公开(公告)号：US20060081894A1

公开(公告)日：2006-04-20

申请号：US10967766

申请日：2004-10-18

申请人： Lindsey Hall

发明人： Lindsey Hall

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/165 ,  H01L21/823412 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.

摘要翻译： 一种形成集成电路晶体管（50）的方法。 该方法提供第一半导体区域（52）并且相对于第一半导体区域形成（110）栅极结构（54×x））在固定位置。 栅极结构具有第一侧壁和第二侧壁（59）。 该方法还形成与第一侧壁和第二侧壁相邻的至少第一层（58××，60×x×）。 该方法还在第一半导体区域中形成（120）至少一个凹部（62×x /），并从栅极结构横向向外延伸。 该方法中的附加步骤首先是氧化（130）所述至少一个凹部，使得在其中形成氧化材料，其次，剥离（140）所述氧化材料的至少一部分，以及第三，形成（160）第二 半导体区域（66×x））。

公开(公告)号：US08940634B2

公开(公告)日：2015-01-27

申请号：US13171657

申请日：2011-06-29

申请人： Brett H. Engel ,  Lindsey Hall ,  David F. Hilscher ,  Randolph F. Knarr ,  Steven R. Soss ,  Jin Z. Wallner

发明人： Brett H. Engel ,  Lindsey Hall ,  David F. Hilscher ,  Randolph F. Knarr ,  Steven R. Soss ,  Jin Z. Wallner

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.

摘要翻译： 在半导体器件中形成重叠触点的方法包括在电介质层中形成第一触点; 蚀刻电介质层以形成与第一接触相邻的凹部，并且在蚀刻介电层的同时去除第一接触的顶部，其中在电介质层中形成凹部之后第一接触的底部保留在电介质层中 ; 以及在与所述第一接触件的底部相邻的所述凹部中形成第二触点，并且在所述第一接触件的底部的顶表面的顶部上形成第二接触。

公开(公告)号：US20080230815A1

公开(公告)日：2008-09-25

申请号：US11726253

申请日：2007-03-21

申请人： Shashank Sureshchandra Ekbote ,  Borna Obradovic ,  Lindsey Hall ,  Craig Huffman ,  Ajith Varghese

发明人： Shashank Sureshchandra Ekbote ,  Borna Obradovic ,  Lindsey Hall ,  Craig Huffman ,  Ajith Varghese

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/76804 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/6659 ,  Y02P80/30

摘要： Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.

摘要翻译： 主要是氧化物而不是氮化物的侧壁间隔物邻近CMOS晶体管的栅极叠层形成。 单独的侧壁间隔物位于栅极堆叠的导电栅电极和晶体管的导电接触之间。 因此，取决于插入的侧壁间隔物的介电常数，可以在栅电极和接触之间产生电容。 因此，从具有比氮化物更低的介电常数的氧化物形成侧壁间隔物减轻了另外可能在这些特征之间产生的电容。 这种电容至少是不利的，因为它可以抑制晶体管的切换速度。 因此，如本文所述的形成侧壁间隔件可以通过减少具有不令人满意的切换速度和/或其它不期望的性能特征的设备的数量来减轻产量损失。