公开(公告)号：US08443225B2

公开(公告)日：2013-05-14

申请号：US13584560

申请日：2012-08-13

Applicant: Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

Inventor： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

IPC: G06F1/12

CPC classification number: G11C7/1045

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Abstract translation: 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

公开(公告)号：US20120303995A1

公开(公告)日：2012-11-29

申请号：US13584560

申请日：2012-08-13

Applicant: Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

Inventor： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

IPC: G06F1/12 ,  G06F1/04

CPC classification number: G11C7/1045

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Abstract translation: 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

公开(公告)号：US20110185218A1

公开(公告)日：2011-07-28

申请号：US12846965

申请日：2010-07-30

Applicant: Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

Inventor： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

IPC: G06F1/04

CPC classification number: G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/50012 ,  G11C2207/2254

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

Abstract translation: 提供了一种方法，系统和计算机程序产品，用于基于训练信号调整存储器设备中的写时序。 例如，该方法可以包括在训练操作模式下配置存储器设备。 该方法还可以包括基于训练信号来确定数据总线上的信号和写入时钟信号之间的写时序窗口。 此外，该方法包括基于写时序窗口来调整数据总线上的信号与写入时钟信号之间的相位差。 存储器件可以基于调整后的相位差来恢复数据总线上的数据。

公开(公告)号：US20110019787A1

公开(公告)日：2011-01-27

申请号：US12509409

申请日：2009-07-24

Applicant: Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

Inventor： Aaron Nygren ,  Ming-Ju Edward Lee ,  Shadi Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael Litt

IPC: H04L7/00 ,  H03K19/096

CPC classification number: G11C7/1045

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Abstract translation: 本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。 根据实施例，在第一IC上提供专用定时引脚。 第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。 在定时引脚上接收到返回信号。 返回信号用于确定是否应由第一个IC调整定时。 在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以便进行确定。 在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

公开(公告)号：US08862966B2

公开(公告)日：2014-10-14

申请号：US12846958

申请日：2010-07-30

Applicant: Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

Inventor： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

IPC: H03M13/00 ,  G06F13/42

CPC classification number: G06F13/4243

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

Abstract translation: 提供了一种方法，系统和计算机程序产品，用于基于错误检测功能的结果来调整存储器件中的写入定时。 例如，该方法可以包括基于错误检测功能的结果来确定数据总线上的信号与写入时钟信号之间的写时序窗口。 该方法还可以包括基于写时序窗口调整数据总线上的信号与写时钟信号之间的相位差。 存储器件可以基于调整后的相位差来恢复数据总线上的数据。

公开(公告)号：US08564326B2

公开(公告)日：2013-10-22

申请号：US13114479

申请日：2011-05-24

Applicant: Xin Liu ,  Arvind Bomdica ,  Ming-Ju Edward Lee

Inventor： Xin Liu ,  Arvind Bomdica ,  Ming-Ju Edward Lee

IPC: H03K5/01

CPC classification number: H03K5/01 ,  H04L25/0272 ,  H04L25/0282

Abstract: A method is provided for selecting at least one of a plurality of slew rate control settings based at least upon a speed of data transmission and receiving input data where the input data is received at the data transmission speed. The method also includes switching the received input data in accordance with the selected at least one of a plurality of slew rate control settings and sending output data at the data transmission speed. Also provided is data driver device that includes at least one activation portion comprising one or more slew rate controls, a voltage-mode driver portion and at least a first current-mode driver portion. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the data driver device. Also provided is a system including the data driver device, a data storage device and a processor device.

Abstract translation: 提供了一种至少根据数据传输的速度选择多个转换速率控制设置中的至少一个并接收以数据传输速度接收输入数据的输入数据的方法。 该方法还包括根据所选择的多个转换速率控制设置中的至少一个切换所接收的输入数据，并以数据传输速度发送输出数据。 还提供了数据驱动器装置，其包括至少一个包括一个或多个转换速率控制的激活部分，电压模式驱动器部分和至少第一电流模式驱动器部分。 还提供了一种用数据编码的计算机可读存储设备，用于使制造设施适配以创建数据驱动器设备。 还提供了包括数据驱动器装置，数据存储装置和处理器装置的系统。

公开(公告)号：US20100238599A1

公开(公告)日：2010-09-23

申请号：US12406705

申请日：2009-03-18

Applicant: Yikai Liang ,  Arvind Bomdica ,  Samudyatha Suryanarayana ,  Gayatri Gopalan ,  Min Xu ,  Xin Liu ,  Ming-Ju Edward Lee

Inventor： Yikai Liang ,  Arvind Bomdica ,  Samudyatha Suryanarayana ,  Gayatri Gopalan ,  Min Xu ,  Xin Liu ,  Ming-Ju Edward Lee

IPC: H02H9/04

CPC classification number: H03K19/00315

Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.

Abstract translation: 描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。 位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路，以保护IC免受过多的电源电压和ESD电压或其他过大的电流条件的影响。 每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。 实施例的保护电路包括高电压IO引脚，降压网络，以将IO引脚上的高电压降低到浮置电压轨上的低电压电平;耦合在浮动电源轨和地之间的第一分流电路， 耦合在浮动电源轨和低电压电源轨之间的均衡器电路，以及通过低压供电轨耦合到均衡器电路的第二分流电路。

公开(公告)号：US08730758B2

公开(公告)日：2014-05-20

申请号：US12490454

申请日：2009-06-24

Applicant: Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Warren Fritz Kruger ,  Xiaoling Xu ,  Toan Duc Pham ,  Aaron John Nygren

Inventor： Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Warren Fritz Kruger ,  Xiaoling Xu ,  Toan Duc Pham ,  Aaron John Nygren

IPC: G11C8/18 ,  G11C7/22 ,  G11C11/4076

CPC classification number: G11C7/22 ,  G06F13/1689 ,  G06F13/4234 ,  G11C7/222 ,  G11C11/4076

Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.

Abstract translation: 提供了一种用于调整存储器件中的写时序的方法和系统。 例如，该方法可以包括接收数据信号，写时钟信号和参考信号。 该方法还可以包括随时间检测参考信号中的相移。 参考信号的相移可用于调整数据信号和写入时钟信号之间的相位差，其中存储器件基于数据信号和写入时钟信号的调整的写入定时从数据信号中恢复数据 。

公开(公告)号：US08489912B2

公开(公告)日：2013-07-16

申请号：US12846972

申请日：2010-07-30

Applicant: Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael John Litt

Inventor： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael John Litt

IPC: G06F1/04

CPC classification number: G06F1/14 ,  G06F1/08 ,  G06F13/1689

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.

Abstract translation: 提供了一种方法，系统和计算机程序产品，用于基于命令协议来调整存储器设备中的写入定时。 例如，该方法可以包括启用写时钟数据恢复（WCDR）操作模式。 该方法还可以包括在WCDR操作模式和存储器件的另一操作模式期间将WCDR数据从处理单元发送到存储器件。 基于WCDR数据中的相移，可以调整数据总线上的信号与写入时钟信号之间的相位差。 此外，该方法可以包括基于数据总线上的信号与写入时钟信号之间调整的相位差在数据总线上传送信号。

公开(公告)号：US08102633B2

公开(公告)日：2012-01-24

申请号：US12406705

申请日：2009-03-18

Applicant: Yikai Liang ,  Arvind Bomdica ,  Samudyatha Suryanarayana ,  Gayatri Gopalan ,  Min Xu ,  Xin Liu ,  Ming-Ju Edward Lee

Inventor： Yikai Liang ,  Arvind Bomdica ,  Samudyatha Suryanarayana ,  Gayatri Gopalan ,  Min Xu ,  Xin Liu ,  Ming-Ju Edward Lee

IPC: H02H9/00 ,  H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22

CPC classification number: H03K19/00315

Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.

Abstract translation: 描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。 位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路，以保护IC免受过多的电源电压和ESD电压或其他过大的电流条件的影响。 每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。 实施例的保护电路包括高电压IO引脚，降压网络，以将IO引脚上的高电压降低到浮置电压轨上的低电压电平;耦合在浮动电源轨和地之间的第一分流电路， 耦合在浮动电源轨和低电压电源轨之间的均衡器电路，以及通过低压供电轨耦合到均衡器电路的第二分流电路。