公开(公告)号：US20030022486A1

公开(公告)日：2003-01-30

申请号：US10097052

申请日：2002-03-13

Applicant: ProMOS Technologies Inc.

Inventor： Joseph Wu

IPC: H01L021/44 ,  H01L021/4763

CPC classification number: H01L21/76804 ,  H01L21/76877

Abstract: The present invention provides a method to prevent short of contact and metal lines. The method is applied in a substrate formed with a number of contact windows. The method is comprised of: (a) forming a first conductive layer in the contact windows without filling up the contact windows; (b) forming liners in the contact windows to reduce the openings of the contact windows; (c) forming liner trenches in the contact windows; and (d) forming a second conduction layer on top of the first conductive layer in the contact windows. According to this invention, shorts between contact windows and metal lines is effectively prevented. Therefore, the product yield is greatly improved.

Abstract translation: 本发明提供一种防止接触不良和金属线的方法。 该方法应用于形成有多个接触窗口的基板中。 该方法包括：（a）在接触窗口中形成第一导电层而不填充接触窗口; （b）在接触窗中形成衬垫以减少接触窗的开口; （c）在接触窗中形成衬垫槽; 和（d）在接触窗口中的第一导电层的顶部上形成第二导电层。 根据本发明，有效地防止了接触窗和金属线之间的短路。 因此，产品产量大大提高。

公开(公告)号：US20240126017A1

公开(公告)日：2024-04-18

申请号：US18046840

申请日：2022-10-14

Applicant: ProMOS Technologies Inc.

Inventor： Ping Ming Liu ,  Hsiao Che Wu

IPC: G02B6/30

CPC classification number: G02B6/305

Abstract: A photonic integrated circuit structure includes a substrate, a waveguide structure and a spot size converter. The waveguide structure is disposed over a surface of the substrate and has a receiving end. The spot size converter includes a concave mirror and a curved mirror. The concave mirror and the curved mirror are opposite to each other and have a common focus. The concave mirror is arranged to reflect a parallel beam from a transmitting end such that a first reflected beam is able to converge at the common focus, and the curved mirror is arranged to reflect the first reflected beam such that a second reflected beam is directed parallel to the receiving end of the waveguide structure.

公开(公告)号：US20040067654A1

公开(公告)日：2004-04-08

申请号：US10265826

申请日：2002-10-07

Applicant: PROMOS TECHNOLOGIES, INC.

Inventor： Chun-Wei Chen ,  Hong-Long Chang ,  Nien-Yu Tsai

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/3065

Abstract: The present invention relates to a method of reducing needle-like defects generated on a wafer rim in an etching process, wherein the etching process using both a photoresist material and hardmask material as a mask. After removing the photoresist material and the hardmask material, said method comprising the steps of: (i) depositing the photoresist material on the wafer again; (ii) performing wafer edge exposure (WEE) to form a ring of the wafer edge; and (iii) performing dry etching to the exposed ring of wafer edge to remove the needle-like defects generated on the wafer edge.

Abstract translation: 本发明涉及一种在蚀刻工艺中减少在晶片边缘上产生的针状缺陷的方法，其中使用光致抗蚀剂材料和硬掩模材料两者的蚀刻工艺作为掩模。 在去除光致抗蚀剂材料和硬掩模材料之后，所述方法包括以下步骤：（i）再次将光致抗蚀剂材料沉积在晶片上; （ii）进行晶片边缘曝光（WEE）以形成晶片边缘的环; 和（iii）对暴露的晶片边缘的环进行干蚀刻以去除在晶片边缘上产生的针状缺陷。

公开(公告)号：US20030087517A1

公开(公告)日：2003-05-08

申请号：US09993749

申请日：2001-11-06

Applicant: ProMOS Technologies, Inc.

Inventor： Brian Lee

IPC: H01L021/4763

CPC classification number: H01L27/10894 ,  H01L21/76897 ,  H01L27/10829 ,  H01L27/10888

Abstract: A consolidated junction contact etch in the fabrication of a DRAM integrated circuit device is described. Semiconductor device structures are provided in and on a substrate wherein the substrate is divided into an active area and a periphery area. The semiconductor device structures are covered with an etch stop layer. A dielectric layer is deposited over the etch stop layer. The dielectric layer is concurrently etched through in the active area to form bit line contact openings, in the periphery area to form substrate contact openings, and to form gate contact openings wherein the etching stops at the etch stop layer. The etch stop layer is etched into to a lesser extent through the substrate contact openings and the bit line contact openings than through the gate contact openings. Then, the etch stop layer is etched through using a directional etch selective to the etch stop layer. The bit line contact openings, substrate contact openings, and gate contact openings are filled with a conducting layer to complete formation of contacts in the fabrication of a DRAM integrated circuit device.

Abstract translation: 描述了在DRAM集成电路器件的制造中的固结结接点蚀刻。 半导体器件结构设置在衬底中和衬底上，其中衬底被分为有源区域和外围区域。 半导体器件结构被蚀刻停止层覆盖。 介电层沉积在蚀刻停止层上。 介电层同时蚀刻穿过有源区域，以形成位线接触开口，在周边区域形成衬底接触开口，并形成栅极接触开口，其中蚀刻在蚀刻停止层处停止。 蚀刻停止层通过基板接触开口和位线接触开口被蚀刻到较小程度，而不是通过栅极接触开口。 然后，通过使用对蚀刻停止层选择性的定向蚀刻蚀刻蚀刻停止层。 位线接触开口，基板接触开口和栅极接触开口填充有导电层，以在DRAM集成电路器件的制造中完成触点的形成。

公开(公告)号：US20030064598A1

公开(公告)日：2003-04-03

申请号：US10195355

申请日：2002-07-15

Applicant: ProMOS Technologies, Inc.

Inventor： Jesse Chung ,  Hsiao-Lei Wang ,  Hung-Kwei Liao

IPC: H01L021/311

CPC classification number: H01L27/10867 ,  H01L21/743

Abstract: A method of forming a buried strap comprising the following sequential steps. A substrate having a pad oxide layer formed thereover is provided. A masking layer is formed over the pad oxide layer. The masking layer, pad oxide layer and substrate are etched to form a trench within the substrate. The trench having an outer sidewall and an upper portion. The upper portion of the trench is lined with a collar. A poly plate is formed within the trench. The poly plate and collar are etched below the substrate to form a recessed poly plate and a recessed collar and exposing a portion of outer sidewall of trench. Ions are implanted into the substrate through exposed outer sidewall of trench by gas phase doping. A SiN sidewall layer is formed over the exposed outer sidewall of trench at a temperature sufficient to diffuse the implanted ions further into the substrate to form the buried strap.

Abstract translation: 一种形成掩埋带的方法，包括以下顺序步骤。 提供了具有形成在其上的衬垫氧化物层的衬底。 在衬垫氧化物层上形成掩模层。 蚀刻掩模层，衬垫氧化物层和衬底以在衬底内形成沟槽。 沟槽具有外侧壁和上部。 沟槽的上部衬有一个领。 在沟槽内形成多晶硅板。 多晶板和套环被蚀刻在基底下方以形成凹入的多晶硅板和凹入的套环，并暴露沟槽外侧壁的一部分。 通过气相掺杂，通过暴露的沟槽的外侧壁将离子注入到衬底中。 在足以将注入的离子进一步扩散到衬底中以形成掩埋带的温度下，在沟槽的暴露的外侧壁上形成SiN侧壁层。

公开(公告)号：US20020176972A1

公开(公告)日：2002-11-28

申请号：US10145718

申请日：2002-05-16

Applicant: ProMOS Technologies, Inc.

Inventor： Tsung-Liang Tsai

IPC: B32B003/00

CPC classification number: H01L22/14 ,  H01L22/34 ,  H01L2924/3011 ,  Y10T428/24843

Abstract: The present invention provides a structure of a contact chain comprising a substrate of a first conductive type, a dielectric layer on the substrate, a plurality of contact structures and two probe pads. The contact structures are connected in series and have two ends. Each contact structure comprises a contact hole in the dielectric layer and conductive material in the contact hole, for electrically contacting with a first doped layer of a second conductive type. The first doped region is formed on the substrate. Two probe pads are coupled to the two ends, respectively. The contact chain further comprises a means for selectively coupling the first doped layer to the substrate. When the first doped layer is not coupled to the substrate, the total resistance of the contact chain can be measured through the two probe pads. During FIB failure analysis, the first doped layer can be forced to couple to the substrate, such that the PN junction between the first doped layer and the substrate will not interfere with the analytic process.

公开(公告)号：US20020096494A1

公开(公告)日：2002-07-25

申请号：US09768523

申请日：2001-01-24

Applicant: ProMOS Technologies Inc.

Inventor： Hungyueh Lu ,  Hong-Long Chang ,  Fang-Fei Liu

IPC: B44C001/22 ,  C23F001/00

CPC classification number: H01L21/02063 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76814

Abstract: A post-cleaning method of a via etching process in the present invention has the steps of: (a) performing a photoresist strip process to remove the photoresist layer; b) performing a dry cleaning process which uses CF4 as the main reactive gas and is operated by dual powers; and (c) performing a water-rinsing process.

Abstract translation: 本发明的通孔蚀刻工艺的后清洗方法具有以下步骤：（a）进行光致抗蚀剂剥离处理以除去光致抗蚀剂层; b）进行使用CF4作为主要反应气体并由双重功率运行的干洗过程; 和（c）进行水冲洗处理。

公开(公告)号：US20020033329A1

公开(公告)日：2002-03-21

申请号：US09725219

申请日：2000-11-29

Applicant: ProMos Technologies Inc.

Inventor： Hsiao-Che Wu

IPC: C23C014/34

CPC classification number: C23C14/564

Abstract: The present invention provides a method using plasma burn-in for maintaining the cleanness within a vacuum chamber of a physical vapor deposition system, thereby reducing particles falling upon a processed wafer. After depositing metal compound films on a specific number of wafers, there will be too many metal compound films accumulated within the vacuum chamber of the physical vapor deposition system and these accumulated films are apt to fall off. The plasma burn-in methods in prior art can not substantially prevent metal compound nodules located on the side surface of a metal target from peeling and thus a more frequent plasma burn-in is required. The present invention discovered through experiments that when the operation pressure of the plasma for plasma burn-in is elevated above 10 mtorr, the distribution of the plasma is ever changed and able to enter the narrow space between the metal target side surface and an inner wall of the vacuum chamber so as to bombard the nodules on the side surface and to deposit a metal film upon the brittle metal compound film within the vacuum chamber for reducing the number of particles falling upon the wafer. In this way the present invention enhances the effect of plasma burn-in, reduces the frequency of plasma burn-in operations and increases the throughput.

Abstract translation: 本发明提供了一种使用等离子体老化来保持物理气相沉积系统的真空室内的清洁度的方法，从而减少落在加工晶片上的颗粒。 在特定数量的晶片上沉积金属化合物膜之后，在物理气相沉积系统的真空室内积聚太多的金属化合物膜，并且这些积聚的膜易于脱落。 现有技术中的等离子体老化方法基本上不能防止位于金属靶的侧表面上的金属化合物结节脱落，因此需要更频繁的等离子体老化。 通过实验发现本发明，当等离子体老化的等离子体的操作压力升高到10mtorr以上时，等离子体的分布变化，能够进入金属靶侧表面和内壁之间的狭窄空间 以便轰击侧表面上的结节，并将金属膜沉积在真空室内的脆性金属化合物膜上，以减少落在晶片上的颗粒数量。 以这种方式，本发明增强了等离子体老化的效果，降低了等离子体老化操作的频率并提高了产量。

公开(公告)号：US20020016035A1

公开(公告)日：2002-02-07

申请号：US09816356

申请日：2001-03-26

Applicant: ProMOS Technologies, Inc.

Inventor： Chao-Chueh Wu ,  Sheng-Fen Chiu ,  Jesse Chung ,  Hsiao-Lei Wang

IPC: H01L021/8242 ,  H01L021/20

CPC classification number: H01L27/1087

Abstract: A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad Si3N4 uniformity for increasing process yields. The method utilizes a thicker pad Si3N4 as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si3N4 layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si3N4 layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si3N4 layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si3N4 layer to provide a more reliable structure for further processing.

Abstract translation: 实现了一种用于在晶片边缘处制造具有减小的沟槽刻面的DRAM电路的改进的深沟槽电容器的方法，并且改善了焊盘Si3N4均匀性以提高工艺产量。 该方法利用较厚的焊盘Si 3 N 4作为用于蚀刻深沟槽的硬掩模的一部分。 然后，在通过一系列工艺步骤形成深沟槽电容器之后，形成浅沟槽隔离（STI）。 该方法利用在较厚的焊盘Si3N4层中蚀刻浅沟槽并进入硅衬底。 将第二绝缘层沉积并抛光（CMP）到焊盘Si3N4层中。 一个关键特征是使用第二掩模来保护衬底中心，同时部分地蚀刻由固化地由CMP产生的衬底边缘处的衬垫Si3N4层的较厚部分。 这使焊盘Si3N4层的不均匀性最小化，以提供用于进一步处理的更可靠的结构。

公开(公告)号：US20040051183A1

公开(公告)日：2004-03-18

申请号：US10330522

申请日：2002-12-27

Applicant: Promos Technologies, Inc.

Inventor： Ming-Sheng Tung ,  Yueh-Chuan Lee

IPC: H01L023/48

CPC classification number: H01L21/76897 ,  H01L23/485 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a self-aligned contact structure with a locally etched conductive layer comprises the steps of: preparing a substrate formed with gate structures comprising a first conductive layer, a second conductive layer, and an insulating layer; depositing a photoresist material layer on the substrate; performing a lithographic step with a bit-line contact node photomask or a bit-line contact photomask to expose a portion of the surface of the substrate; etching the exposed second conductive layer with an etchant; removing the remaining photoresist material layer; forming a sidewall spacer on the sidewalls of each gate structure; forming a dielectric layer to cover the substrate; and performing lithographic and etching steps to remove the dielectric layer and to form self-aligned contact structure.

Abstract translation: 用局部蚀刻的导电层形成自对准接触结构的方法包括以下步骤：制备由栅极结构形成的衬底，该栅极结构包括第一导电层，第二导电层和绝缘层; 在基板上沉积光致抗蚀剂材料层; 用位线接触节点光掩模或位线接触光掩模执行光刻步骤以暴露所述衬底表面的一部分; 用蚀刻剂蚀刻暴露的第二导电层; 去除剩余的光致抗蚀剂材料层; 在每个栅极结构的侧壁上形成侧壁间隔物; 形成介电层以覆盖基板; 并执行光刻和蚀刻步骤以去除介电层并形成自对准接触结构。