公开(公告)号：US20110103143A1

公开(公告)日：2011-05-05

申请号：US12986802

申请日：2011-01-07

Applicant: Rajiv Yadav RANJAN ,  Roger Klas MALMHALL ,  Parviz KESHTBOD

Inventor： Rajiv Yadav RANJAN ,  Roger Klas MALMHALL ,  Parviz KESHTBOD

IPC: G11C11/14 ,  H01L29/82

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C19/0808 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.

Abstract translation: 公开了一种包括自由层，两个堆叠和磁性隧道结的多状态低电流切换磁存储元件（磁存储元件）。 堆叠和磁性隧道结设置在自由层的表面上，磁性隧道结位于堆叠之间。 堆叠在自由层内引导磁畴，产生自由层畴壁。 从堆栈传递到堆栈的电流推动域壁，重新定位自由层内的域壁。 畴壁相对于磁性隧道结的位置对应于唯一的电阻值，并且将电流从堆叠传递到磁性隧道结读取磁存储元件的电阻。 因此，可以通过移动域壁来实现唯一的记忆状态。

公开(公告)号：US20110089511A1

公开(公告)日：2011-04-21

申请号：US12975304

申请日：2010-12-21

Applicant: Parviz KESHTBOD ,  Roger Klas MALMHALL ,  Rajiv Yadav RANJAN

Inventor： Parviz KESHTBOD ,  Roger Klas MALMHALL ,  Rajiv Yadav RANJAN

IPC: H01L29/82 ,  H01L21/8246

CPC classification number: H01L43/12 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

Abstract: A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer.

Abstract translation: 制造磁性随机存取存储单元的方法包括在晶片的顶部形成磁性隧道结（MTJ），在MTJ的顶部上沉积氧化物，在氧化物层的顶部上沉积光致抗蚀剂层，形成沟槽 所述光刻胶层和所述沟槽的宽度与所述MTJ的宽度基本相同的氧化物层。 然后，除去光致抗蚀剂层，并且在沟槽中的氧化物层的顶部上沉积硬掩模层，并且平坦化晶片以去除不在沟槽中的硬掩模层的部分以使顶部基本上平坦 的氧化物层和硬质层。 蚀刻剩余的氧化物层，并蚀刻MTJ以除去未被硬掩模层覆盖的MTJ的部分。

公开(公告)号：US20090218645A1

公开(公告)日：2009-09-03

申请号：US12397255

申请日：2009-03-03

Applicant: Rajiv Yadav RANJAN ,  Parviz KESHTBOD

Inventor： Rajiv Yadav RANJAN ,  Parviz KESHTBOD

IPC: H01L29/82

CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/5607 ,  G11C2211/5615 ,  H01L27/228 ,  H01L43/08 ,  Y10S977/933 ,  Y10S977/935

Abstract: A multi-state spin-torque transfer magnetic random access memory (STTMRAM) is formed on a film and includes a first magnetic tunneling junctions (MTJ) having a first fixed layer, a first sub-magnetic tunnel junction (sub-MTJ) layer and a first free layer. The first fixed layer and first free layer each have a first magnetic anisotropy. The STTMRAM further includes a non-magnetic spacing layer formed on top of the first MTJ layer and a second MTJ formed on top of the non-magnetic spacing layer. The second MTJ has a second fixed layer, a second sub-MTJ layer and a second free layer. The second fixed and second free layers each have a second magnetic anisotropy, wherein at least one of the first or second magnetic anisotropy is perpendicular to the plane of the film.

Abstract translation: 在薄膜上形成多态自旋转矩传递磁随机存取存储器（STTMRAM），其包括具有第一固定层，第一子磁性隧道结（sub-MTJ）层和第一子磁隧道结（sub-MTJ）层的第一磁隧道结（MTJ） 第一个自由层。 第一固定层和第一自由层各自具有第一磁各向异性。 STTMRAM还包括形成在第一MTJ层的顶部上的非磁性间隔层和形成在非磁性间隔层的顶部上的第二MTJ。 第二MTJ具有第二固定层，第二子MTJ层和第二自由层。 第二固定和第二自由层各自具有第二磁各向异性，其中第一或第二磁各向异性中的至少一个垂直于膜的平面。

公开(公告)号：US6018265A

公开(公告)日：2000-01-25

申请号：US52038

申请日：1998-03-30

Applicant: Parviz Keshtbod

Inventor： Parviz Keshtbod

IPC: G11C16/06 ,  G05F1/10 ,  G05F3/02 ,  G05F3/24

CPC classification number: G05F3/247

Abstract: The present invention includes a circuit for deriving a reference signal having a reference voltage from a system voltage source having a system voltage level and for regulating the reference voltage level. The circuit includes an output sub-circuit, a reference generator sub-circuit, a regulator sub-circuit, a translator sub-circuit, and a low pass filter sub-circuit. The output sub-circuit, which is coupled to the system voltage source, is responsive to a voltage control signal, and is operative to generate the reference signal wherein the reference voltage level is less than or equal to the system voltage level. The reference generator sub-circuit is responsive to the reference signal and is operative to generate a prime voltage level which remains substantially unaffected by fabrication process variations, temperature variations and variations in the reference signal. The regulator sub-circuit is responsive to the reference signal and the prime voltage level and is operative to generate the voltage control signal. The translator sub-circuit is coupled to the system voltage source and functions to amplify the voltage control signal. The low pass filter sub-circuit is used for filtering the voltage control signal. The output sub-circuit includes an output transistor having its gate coupled to receive the voltage control signal, its source connected to the system voltage source, and its drain connected to an output terminal at which the reference signal is provided.

Abstract translation: 本发明包括用于从具有系统电压电平的系统电压源导出具有参考电压并用于调节参考电压电平的参考信号的电路。 电路包括输出子电路，参考发生器子电路，调节器子电路，转换器子电路和低通滤波器子电路。 耦合到系统电压源的输出子电路响应于电压控制信号，并且可操作地产生参考信号，其中参考电压电平小于或等于系统电压电平。 参考发生器子电路响应于参考信号，并且可操作地产生主要电压电平，其基本上不受制造工艺变化，温度变化和参考信号变化的影响。 稳压器子电路响应于参考信号和主电压电平，并且可操作地产生电压控制信号。 转换器子电路耦合到系统电压源并且用于放大电压控制信号。 低通滤波器子电路用于对电压控制信号进行滤波。 输出子电路包括输出晶体管，其输出晶体管的栅极被耦合以接收电压控制信号，其源极连接到系统电压源，其漏极连接到提供参考信号的输出端子。

公开(公告)号：US5776787A

公开(公告)日：1998-07-07

申请号：US650785

申请日：1996-05-20

Applicant: Parviz Keshtbod

Inventor： Parviz Keshtbod

IPC: H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The cell is adapted so that the source for each cell within the array is the source of an adjacent cell and the drain is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a metal, preferably tungsten or a tungsten alloy. The field oxide is selectively removed. A gate oxide is grown and a first polysilicon layer is formed and then etched to form spacers along the edges of the metal/second insulator structure. The first polysilicon is selectively etched and a tunneling insulator layer is formed thereover. A second polysilicon layer is formed over the tunneling insulator.

Abstract translation: 闪存EPROM单元在编程期间通过在浮动栅极和位线之间提供垂直耦合而具有减小的单元尺寸。 擦除操作是通过将电子从Poly间隔物的尖端引导到控制栅极进行的。 单元被适配成使得阵列内的每个单元的源极是相邻单元的源极，漏极是另一相邻单元的漏极。 通过在优选为场氧化物的第一绝缘体中的开口将漏区形成为衬底而形成电池。 第二绝缘体沉积在第一绝缘体上方，在衬底上并且沿着开口的侧壁，并且优选地是薄层，使得开口被薄绝缘层覆盖。 绝缘开口填充有金属，优选钨或钨合金。 有选择地去除场氧化物。 生长栅极氧化物并形成第一多晶硅层，然后蚀刻以沿着金属/第二绝缘体结构的边缘形成间隔物。 选择性地蚀刻第一多晶硅，并在其上形成隧穿绝缘体层。 在隧道绝缘体上形成第二多晶硅层。

公开(公告)号：US5476801A

公开(公告)日：1995-12-19

申请号：US383090

申请日：1995-02-03

Applicant: Parviz Keshtbod

Inventor： Parviz Keshtbod

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/441

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/4232 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The cell is adapted so that the source for each cell within the array is the source of an adjacent cell and the drain is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a first doped polysilicon layer. The field oxide is selectively removed. A gate oxide is grown and a second polysilicon layer is formed and then etched to form spacers along the edges of the first polysilicon/second insulator structure. The second polysilicon is selectively etched and a tunneling insulator layer is formed thereover. A third polysilicon layer is formed over the tunneling insulator.

Abstract translation: 闪存EPROM单元在编程期间通过在浮动栅极和位线之间提供垂直耦合而具有减小的单元尺寸。 擦除操作是通过将电子从Poly间隔物的尖端引导到控制栅极进行的。 单元被适配成使得阵列内的每个单元的源极是相邻单元的源极，漏极是另一相邻单元的漏极。 通过在优选为场氧化物的第一绝缘体中的开口将漏区形成为衬底而形成电池。 第二绝缘体沉积在第一绝缘体上方，在衬底上并且沿着开口的侧壁，并且优选地是薄层，使得开口被薄绝缘层覆盖。 绝缘开口填充有第一掺杂多晶硅层。 有选择地去除场氧化物。 生长栅极氧化物并形成第二多晶硅层，然后蚀刻以沿着第一多晶硅/第二绝缘体结构的边缘形成间隔物。 选择性地蚀刻第二多晶硅，并在其上形成隧穿绝缘体层。 在隧道绝缘体上形成第三多晶硅层。

公开(公告)号：US08574928B2

公开(公告)日：2013-11-05

申请号：US13443818

申请日：2012-04-10

Applicant: Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

Inventor： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

IPC: H01L21/00

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

Abstract translation: 描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

公开(公告)号：US20130244344A1

公开(公告)日：2013-09-19

申请号：US13610587

申请日：2012-09-11

Applicant: Roger Klas Malmhall ,  Kimihiro Satoh ,  Jing Zhang ,  Parviz Keshtbod ,  Rajiv Yadav Ranjan

Inventor： Roger Klas Malmhall ,  Kimihiro Satoh ,  Jing Zhang ,  Parviz Keshtbod ,  Rajiv Yadav Ranjan

IPC: H01L43/12

CPC classification number: H01L43/12 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/161 ,  H01L27/228

Abstract: Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited.

Abstract translation: 描述了使用两个正交线图案化步骤制造MTJ阵列的方法。 描述了使用用于一个或两个正交线图案化步骤的自对准双图案化方法来实现特征尺寸为最小光刻特征尺寸（F）的一半的MTJ的致密阵列的实施例。 在一组实施例中，选择提供掩模功能的层叠层的材料和厚度，使得在初始掩模焊盘组被图案化之后，一系列蚀刻步骤逐渐地将掩模焊盘形状传递通过多个掩模 通过所有的MTJ单元层的层和下层形成完整的MTJ柱。 在另一组实施例中，在沉积顶部电极层之前，将MTJ / BE叠层图案化成平行线。

公开(公告)号：US08488376B2

公开(公告)日：2013-07-16

申请号：US13476879

申请日：2012-05-21

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

IPC: G11C11/14

CPC classification number: B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3236 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/228 ,  H01L43/08

Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.

Abstract translation: 非易失性磁存储元件包括多个层，其中之一是分级的自由层。 分级自由层可以包括各种元素，其中每个元素具有不同的各向异性，或者其可以包括非磁性化合物和磁性区域，其中非磁性化合物形成梯度含量形成独特的形状，例如锥形，菱形或其它形状，并且其厚度 是基于磁性化合物的反应性。

公开(公告)号：US08477529B2

公开(公告)日：2013-07-02

申请号：US13623054

申请日：2012-09-19

Applicant: Parviz Keshtbod ,  Ebrahim Abedifard

Inventor： Parviz Keshtbod ,  Ebrahim Abedifard

IPC: G11C11/00

CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/105 ,  H01L27/228

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

Abstract translation: 磁性随机存取存储器（MRAM）单元包括嵌入式MRAM和存取晶体管。 嵌入式MRAM形成在多个金属插入层间电介质（ILD）层中，每个层包括分散在其中的金属并形成在存取晶体管的顶部。 在位于靠近位线的ILD层中形成的金属的顶部上形成磁隧道结（MTJ）。 MTJ掩模用于对MTJ进行图案蚀刻，以暴露MTJ。 最终，在位线顶部形成金属并延伸以接触MTJ。