Data processing apparatus and method for switching a workload between first and second processing circuitry

    公开(公告)号:US20110213935A1

    公开(公告)日:2011-09-01

    申请号:US12659235

    申请日:2010-03-01

    IPC分类号: G06F15/76 G06F12/08 G06F9/02

    摘要: A data processing apparatus and method are provided for switching performance of a workload between two processing circuits. The data processing apparatus has first processing circuitry which is architecturally compatible with second processing circuitry, but with the first processing circuitry being micro-architecturally different from the second processing circuitry. At any point in time, a workload consisting of at least one application and at least one operating system for running that application is performed by one of the first processing circuitry and the second processing circuitry. A switch controller is responsive to a transfer stimulus to perform a handover operation to transfer performance of the workload from source processing circuitry to destination processing circuitry, with the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry. The switch controller is arranged, during the handover operation, to cause the source processing circuitry to make its current architectural state available to the destination processing circuitry, the current architectural state being that state not available from shared memory shared between the first and second processing circuitry at a time the handover operation is initiated, and that is necessary for the destination processing circuitry to successfully take over performance of the workload from the source processing circuitry. Further, the source processing circuitry and second processing circuitry implement an accelerated mechanism to make the current architectural state available to the destination processing circuitry without routing of the current architectural state via the shared memory. Since the accelerated mechanism is quick and energy efficient, it increases the number of situations it which it is energy efficient to make the switch from one processing circuitry to the other.

    Data processing apparatus and method for identifying sequences of instructions
    12.
    发明授权
    Data processing apparatus and method for identifying sequences of instructions 有权
    用于识别指令序列的数据处理装置和方法

    公开(公告)号:US07831815B2

    公开(公告)日:2010-11-09

    申请号:US12068447

    申请日:2008-02-06

    摘要: A data processing apparatus is provided comprising a processing unit for executing instructions, a cache structure for storing instructions retrieved from memory for access by the processing unit, and profiling logic for identifying a sequence of instructions that is functionally equivalent to an accelerator instruction. When such a sequence of instructions is identified, the equivalent accelerator instruction is stored in the cache structure as a replacement for the first instruction of the sequence, with the remaining instructions in the sequence of instructions being stored unchanged. The accelerator instruction includes an indication to cause the processing unit to skip the remainder of the sequence when executing the accelerator instruction.

    摘要翻译: 提供了一种数据处理装置,包括用于执行指令的处理单元,用于存储由存储器检索的用于由处理单元访问的指令的高速缓存结构,以及用于识别在功能上等同于加速器指令的指令序列的分析逻辑。 当识别出这样的指令序列时,将等效加速器指令作为序列的第一指令的替换存储在高速缓存结构中,指令序列中的剩余指令被保持不变。 加速器指令包括当执行加速器指令时使处理单元跳过序列的剩余部分的指示。

    Pre-decode checking for pre-decoded instructions that cross cache line boundaries
    13.
    发明申请
    Pre-decode checking for pre-decoded instructions that cross cache line boundaries 有权
    预先解码检查跨越高速缓存线边界的预解码指令

    公开(公告)号:US20100017580A1

    公开(公告)日:2010-01-21

    申请号:US12458512

    申请日:2009-07-14

    IPC分类号: G06F9/30 G06F9/312

    摘要: A data processing and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from a memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in the cache for access by the processing circuitry. If a pre-decoded instruction crosses a cache line boundary, then checking circuitry in respect of selected types of pre-decoded instruction checks for consistency between the first portion of the pre-decoded instruction stored within a first cache line and a contiguous second portion of the pre-decoded instruction stored within a second cache line. If this consistency check is passed such that the two portions are self-consistent, then the pre-decoded instruction can be further decoded and issued. If the consistency check is failed, or the pre-decoded instruction is not of a type for which consistency checking is supported, then re-generation of the pre-decoded instruction is triggered.

    摘要翻译: 提供用于预解码指令的数据处理和方法。 数据处理装置具有用于接收从存储器取出的指令并用于执行预解码操作以产生相应的预解码指令的预解码电路,然后存储在缓存器中以供处理电路访问。 如果预解码指令跨越高速缓存线边界,则检查电路对所选择类型的预解码指令检查,以确定存储在第一高速缓存行内的预解码指令的第一部分与第一高速缓存行的连续第二部分之间的一致性 所述预解码指令存储在第二高速缓存行内。 如果通过这种一致性检查使得两部分是自相一致的,则可以进一步解码和发出预解码指令。 如果一致性检查失败,或者预解码指令不是支持一致性检查的类型,则触发预解码指令的再生成。

    Data processing apparatus and method for handling instructions to be executed by processing circuitry
    14.
    发明申请
    Data processing apparatus and method for handling instructions to be executed by processing circuitry 有权
    用于处理由处理电路执行的指令的数据处理装置和方法

    公开(公告)号:US20090249033A1

    公开(公告)日:2009-10-01

    申请号:US12314095

    申请日:2008-12-03

    IPC分类号: G06F9/312 G06F9/30 G06F12/08

    摘要: A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.

    摘要翻译: 提供了一种用于处理由处理电路执行的指令的数据处理装置和方法。 处理电路具有多个处理器状态,每个处理器状态具有与其相关联的不同指令集。 预解码电路接收从存储器取出的指令,并执行预解码操作以产生相应的预解码指令,然后将那些预先解码的指令存储在高速缓存中以供处理电路访问。 预解码电路在假设处理器状态下执行预解码操作,并且高速缓存被配置为存储与预解码指令相关联的推测性处理器状态的指示。 如果处理电路的当前处理器状态与存储在该指令的高速缓存中的推测性处理器状态的指示相匹配,则处理电路然后被布置为仅使用来自高速缓存的相应的预解码指令来执行序列中的指令。 这提供了一种用于检测由于处理器状态的不正确假设而被预解码操作损坏的指令的简单而有效的机制。

    Data processing apparatus and method for identifying sequences of instructions
    15.
    发明申请
    Data processing apparatus and method for identifying sequences of instructions 有权
    用于识别指令序列的数据处理装置和方法

    公开(公告)号:US20090198978A1

    公开(公告)日:2009-08-06

    申请号:US12068447

    申请日:2008-02-06

    IPC分类号: G06F9/30

    摘要: A data processing apparatus is provided comprising a processing unit for executing instructions, a cache structure for storing instructions retrieved from memory for access by the processing unit, and profiling logic for identifying a sequence of instructions that is functionally equivalent to an accelerator instruction. When such a sequence of instructions is identified, the equivalent accelerator instruction is stored in the cache structure as a replacement for the first instruction of the sequence, with the remaining instructions in the sequence of instructions being stored unchanged. The accelerator instruction includes an indication to cause the processing unit to skip the remainder of the sequence when executing the accelerator instruction.

    摘要翻译: 提供了一种数据处理装置,包括用于执行指令的处理单元,用于存储由存储器检索的用于由处理单元访问的指令的高速缓存结构,以及用于识别在功能上等同于加速器指令的指令序列的分析逻辑。 当识别出这样的指令序列时,将等效加速器指令作为序列的第一指令的替换存储在高速缓存结构中,指令序列中的剩余指令被保持不变。 加速器指令包括当执行加速器指令时使处理单元跳过序列的剩余部分的指示。

    Data processing apparatus and method for transferring workload between source and destination processing circuitry
    16.
    发明授权
    Data processing apparatus and method for transferring workload between source and destination processing circuitry 有权
    用于在源和目的地处理电路之间传送工作负载的数据处理装置和方法

    公开(公告)号:US08533505B2

    公开(公告)日:2013-09-10

    申请号:US12659230

    申请日:2010-03-01

    IPC分类号: G06F1/32 G06F12/00 G06F12/08

    摘要: In response to a transfer stimulus, performance of a processing workload is transferred from a source processing circuitry to a destination processing circuitry, in preparation for the source processing circuitry to be placed in a power saving condition following the transfer. To reduce the number of memory fetches required by the destination processing circuitry following the transfer, a cache of the source processing circuitry is maintained in a powered state for a snooping period. During the snooping period, cache snooping circuitry snoops data values in the source cache and retrieves the snoop data values for the destination processing circuitry.

    摘要翻译: 响应于传输刺激,处理工作负载的性能从源处理电路传送到目的地处理电路,以准备将源处理电路置于转移之后的省电状态。 为了减少转移之后目的地处理电路所需的存储器获取数量,源处理电路的高速缓存保持在用于窥探期的供电状态。 在窥探期间,缓存窥探电路监听源缓存中的数据值,并检索目标处理电路的窥探数据值。

    Pre-decode checking for pre-decoded instructions that cross cache line boundaries
    18.
    发明授权
    Pre-decode checking for pre-decoded instructions that cross cache line boundaries 有权
    预先解码检查跨越高速缓存线边界的预解码指令

    公开(公告)号:US07925867B2

    公开(公告)日:2011-04-12

    申请号:US12458512

    申请日:2009-07-14

    IPC分类号: G06F9/30

    摘要: A data processing and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from a memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in the cache for access by the processing circuitry. If a pre-decoded instruction crosses a cache line boundary, then checking circuitry in respect of selected types of pre-decoded instruction checks for consistency between the first portion of the pre-decoded instruction stored within a first cache line and a contiguous second portion of the pre-decoded instruction stored within a second cache line. If this consistency check is passed such that the two portions are self-consistent, then the pre-decoded instruction can be further decoded and issued. If the consistency check is failed, or the pre-decoded instruction is not of a type for which consistency checking is supported, then re-generation of the pre-decoded instruction is triggered.

    摘要翻译: 提供用于预解码指令的数据处理和方法。 数据处理装置具有用于接收从存储器取出的指令并用于执行预解码操作以产生相应的预解码指令的预解码电路,然后存储在缓存器中以供处理电路访问。 如果预解码指令跨越高速缓存线边界,则检查电路对所选择的预解码指令类型的类型进行检查,以确定存储在第一高速缓存行内的预解码指令的第一部分与第一高速缓存行的连续第二部分之间的一致性 所述预解码指令存储在第二高速缓存行内。 如果通过这种一致性检查使得两部分是自相一致的,则可以进一步解码和发出预解码指令。 如果一致性检查失败,或者预解码指令不是支持一致性检查的类型,则触发预解码指令的再生成。

    Data processing apparatus and method for pre-decoding instructions
    19.
    发明申请
    Data processing apparatus and method for pre-decoding instructions 有权
    用于预解码指令的数据处理装置和方法

    公开(公告)号:US20090187744A1

    公开(公告)日:2009-07-23

    申请号:US12010316

    申请日:2008-01-23

    IPC分类号: G06F9/30

    摘要: A data processing apparatus and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in a cache for access by processing circuitry. For a first set of instructions, each instruction comprises a plurality of instruction portions, and the pre-decoding circuitry generates a corresponding pre-decoded instruction comprising a plurality of pre-decoded instruction portions. If when applying the pre-decoding operation to an instruction in the first set, the pre-decoding circuitry does not have access to all of the plurality of instruction portions of that instruction, the pre-decoding circuitry is arranged to provide in association with at least one pre-decoded instruction portion that it does generate, an indication that the pre-decoded instruction portion relates to an incomplete pre-decoding operation. This provides a simple and effective mechanism for detecting situations where a pre-decoded instruction as later read from the cache may have become corrupted by the pre-decoding operation, and accordingly should not be relied upon.

    摘要翻译: 提供了用于对指令进行解码的数据处理装置和方法。 数据处理装置具有预解码电路,用于接收从存储器取出的指令,并用于执行预解码操作,以产生相应的预解码指令,然后存储在高速缓存中以供处理电路访问。 对于第一组指令,每个指令包括多个指令部分,并且预解码电路生成包括多个预解码指令部分的对应的预解码指令。 如果当将预解码操作应用于第一组中的指令时,预解码电路不具有对该指令的所有多个指令部分的访问权,则预解码电路被布置为提供与在 其确实生成的至少一个预解码指令部分,预解码指令部分与不完整的预解码操作有关的指示。 这提供了一种用于检测其中稍后从缓存读取的预解码指令可能已经被预解码操作损坏的情况的简单且有效的机制,因此不应被依赖。

    Data processing apparatus and method for handling instructions to be executed by processing circuitry

    公开(公告)号:US20090187741A1

    公开(公告)日:2009-07-23

    申请号:US12010305

    申请日:2008-01-23

    IPC分类号: G06F9/30

    摘要: A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.