公开(公告)号：US4320455A

公开(公告)日：1982-03-16

申请号：US100028

申请日：1979-12-03

申请人： William E. Woods ,  Philip E. Stanley ,  Thomas S. Hirsch

发明人： William E. Woods ,  Philip E. Stanley ,  Thomas S. Hirsch

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F9/36

CPC分类号： G06F9/4881 ,  G06F9/546

摘要： One or more queue structures in a data processing system may include a threaded list of frames which are enqueued or dequeued from the list in accordance with four instructions wherein each list is tied to a so-called lock or control frame with synchronization for multiple processing units. Multiple lock frames and accordingly multiple lists of frames may be coupled in the system for the purpose of accomplishing the various tasks necessary.

摘要翻译： 数据处理系统中的一个或多个队列结构可以包括根据四个指令从列表排队或出队的帧的线程列表，其中每个列表被绑定到所谓的锁定或控制帧，具有多个处理单元的同步 。 多个锁帧和相应的多个帧列表可以耦合在系统中以实现所需的各种任务。

公开(公告)号：US4451883A

公开(公告)日：1984-05-29

申请号：US326260

申请日：1981-12-01

申请人： Philip E. Stanley ,  William E. Woods ,  Richard A. Lemay ,  David E. Cushing

发明人： Philip E. Stanley ,  William E. Woods ,  Richard A. Lemay ,  David E. Cushing

IPC分类号： G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F9/22 ,  G06F9/315 ,  G06F9/12 ,  G06F9/20

CPC分类号： G06F9/30032 ,  G06F9/30167

摘要： A data processing system includes a memory subsystem for storing operands and instructions and a central processing unit (CPU) for manipulating the operands by executing the instructions. The CPU includes a control store for generating signals for controlling the CPU operation. Shifters made up of multiplexers shift operands between an outer bus and a write bus in response to control store signals. The multiplexers shift the operands left or right 1, 2 or 4-bit positions including open shifts and circular shifts and also perform byte position shifting and twinning.

摘要翻译： 数据处理系统包括用于存储操作数和指令的存储器子系统和用于通过执行指令来操纵操作数的中央处理单元（CPU）。 CPU包括用于产生用于控制CPU操作的信号的控制存储器。 由复用器组成的移位器响应于控制存储信号在外部总线和写入总线之间移动操作数。 多路复用器将操作数向左或向右移位1,2或4位位置，包括开位移和循环移位，并且还执行字节位移和孪生。

公开(公告)号：US4438493A

公开(公告)日：1984-03-20

申请号：US280720

申请日：1981-07-06

申请人： David E. Cushing ,  Philip E. Stanley

发明人： David E. Cushing ,  Philip E. Stanley

IPC分类号： G06F12/06 ,  G06F12/04 ,  G06F13/00 ,  G11C17/00

CPC分类号： G06F12/04 ,  G11C17/00

摘要： A technique and apparatus for storing data and addressing stored data in a memory from which multiple words of data are to be retrieved in parallel is disclosed. The memory is addressed by providing the address of the first of N consecutive words to be retrieved in parallel. The data is stored in memory in physical data words which contain N logical data words such that the addressing of one physical data word will result in N logical data words being read in parallel from the memory. Each physical data word contains the contents of the logical data word having the same address as that of the physical data word in its leftmost position followed in the next right position by the contents of the logical data word having the next higher address, and so on until the rightmost position of the physical data word contains the contents of the logical data word with an address equal to the physical data word address plus N-1. This results in the contents of each logical data word being stored N times in the memory, but eliminates the need for data alignment as the N logical data words are read in parallel from the memory.

摘要翻译： 公开了一种用于存储数据并将存储的数据寻址到并行地检索多个数据字的存储器中的技术和装置。 通过提供并行检索的N个连续字中的第一个字的地址来寻址存储器。 将数据存储在存储有包含N个逻辑数据字的物理数据字中，使得一个物理数据字的寻址将导致从存储器并行读取的N个逻辑数据字。 每个物理数据字包含具有与其最左侧位置的物理数据字的地址相同的地址的逻辑数据字的内容，紧接在下一个右侧位置，具有具有下一个较高地址的逻辑数据字的内容，等等 直到物理数据字的最右边位置包含地址等于物理数据字地址加N-1的逻辑数据字的内容。 这导致每个逻辑数据字的内容在存储器中被存储N次，但是当N个逻辑数据字从存储器并行读取时，不需要数据对准。

公开(公告)号：US4079451A

公开(公告)日：1978-03-14

申请号：US674698

申请日：1976-04-07

申请人： William E. Woods ,  Philip E. Stanley

发明人： William E. Woods ,  Philip E. Stanley

IPC分类号： G06F9/46 ,  G06F9/305 ,  G06F9/308 ,  G06F9/34 ,  G06F12/04 ,  G06F9/00

CPC分类号： G06F9/30018 ,  G06F12/04

摘要： A data processing system for providing word, byte or bit addressing. A word location in a memory device may be addressed based upon the contents of a base address register. Indirect addressing may be provided to another word location based upon a word index value in an index register. Effective byte or bit addressing of the addressed word is provided in response to byte and bit index values which are produced by means of the index register. An instruction word indicates the type of addressing and directs the use of different control words included in a control storage device in order to implement the desired operation.

摘要翻译： 一种用于提供字，字节或位寻址的数据处理系统。 可以基于基地址寄存器的内容来寻址存储器设备中的字位置。 可以基于索引寄存器中的单词索引值将间接寻址提供给另一单词位置。 响应于通过索引寄存器产生的字节和位索引值，提供寻址字的有效字节或位寻址。 指令字指示寻址的类型并指示使用包括在控制存储设备中的不同控制字，以便实现期望的操作。

公开(公告)号：US4524416A

公开(公告)日：1985-06-18

申请号：US430488

申请日：1982-09-30

申请人： Philip E. Stanley ,  Piotr Szorc

发明人： Philip E. Stanley ,  Piotr Szorc

IPC分类号： G06F9/34 ,  G06F15/16

CPC分类号： G06F9/34

摘要： In a data processing system, a stack mechanism creates a stack of operands in a series of memory locations. The memory locations are grouped into stack frames corresponding to the operands included within individual procedures executed by a processing unit of the data processing system. The stack has a maximum number of allocatable storage locations with the actual physical size of the stack being equal to the total number of operands stored therein. The size of the stack is dynamically alterable to conserve usable storage locations in the memory and accessing of operands within a stack frame can be relative to the top or bottom of the stack frame.

摘要翻译： 在数据处理系统中，堆栈机制在一系列存储单元中创建一组操作数。 存储器位置被分组成与由数据处理系统的处理单元执行的各个过程中包括的操作数相对应的堆栈帧。 堆栈具有最大数量的可分配存储位置，堆栈的实际物理大小等于其中存储的操作数的总数。 堆栈的大小可动态地改变以节省存储器中的可用存储位置，并且访问堆栈帧内的操作数可以相对于堆栈帧的顶部或底部。

公开(公告)号：US4472773A

公开(公告)日：1984-09-18

申请号：US302897

申请日：1981-09-16

申请人： Philip E. Stanley ,  William E. Woods ,  Richard A. Lemay

发明人： Philip E. Stanley ,  William E. Woods ,  Richard A. Lemay

IPC分类号： G06F9/30 ,  G06F1/00

CPC分类号： G06F9/30

摘要： A decoding logic system in a logic control system of a data processing system is disclosed, wherein the data processing system is comprized of a main memory unit communicating with the logic control system by way of a common communication bus, and wherein the logic control system and a CPU (central processing unit) communicate by way of a local communication bus. In response to a CPU request, CPU instructions stored in the main memory unit are received by the logic decoding system, and presented to the CPU in such a manner as to accommodate both memory bit and CPU computed bit modifications to the instructions during instruction execution, while avoiding interruptions in CPU activity caused by information transfer delays internal to the logic decoding system. Instruction modification also may be effected by incrementing or decrementing the instructions under firmware control.

摘要翻译： 公开了一种数据处理系统的逻辑控制系统中的解码逻辑系统，其中数据处理系统由与公共通信总线与逻辑控制系统通信的主存储单元组成，其中逻辑控制系统和 CPU（中央处理单元）通过本地通信总线进行通信。 响应于CPU请求，存储在主存储器单元中的CPU指令由逻辑解码系统接收，并且以在指令执行期间容纳存储器位和CPU计算的位修改的方式呈现给CPU， 同时避免在逻辑解码系统内部的信息传输延迟引起的CPU活动中断。 也可以通过在固件控制下增加或减少指令来实现指令修改。

公开(公告)号：US4445172A

公开(公告)日：1984-04-24

申请号：US221853

申请日：1980-12-31

申请人： Arthur Peters ,  Philip E. Stanley

发明人： Arthur Peters ,  Philip E. Stanley

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0851

摘要： A cache memory including an even data store for storing data words associated with even address numbers and an odd data store for storing data words associated with odd address numbers, a local bus for transferring a low order data word and a high order data word simultaneously from the cache memory to a system element requesting the transfer of a pair of data words through the supplying of a single address number request, and a data steering multiplexer for supplying the data word associated with the memory request number, as outputted from either the odd or even cache data store to the low order data word transfer portion of the local bus and the other of the pair of data words outputted from the odd or even data store to the high order data word transfer portion of the local bus.

摘要翻译： 一种高速缓冲存储器，包括用于存储与偶数地址号码相关联的数据字的偶数数据存储器和用于存储与奇数地址号码相关联的数据字的奇数数据存储器，用于同时从低位数据字传输低位数据字的本地总线和高位数据字 高速缓冲存储器通过提供单个地址号码请求而请求传送一对数据字的系统元件，以及用于提供与存储器请求号相关联的数据字的数据导向复用器，从奇数或 甚至高速缓存数据存储到本地总线的低阶数据字传送部分，以及从奇数或偶数数据存储器输出到本地总线的高位数据字传送部分的一对数据字中的另一个。

公开(公告)号：US4414637A

公开(公告)日：1983-11-08

申请号：US224727

申请日：1981-01-13

申请人： Philip E. Stanley

发明人： Philip E. Stanley

IPC分类号： H03K5/06 ,  H03K5/04 ,  H03K5/159

CPC分类号： H03K5/06

摘要： A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a first delay line coupled to an inverter by using a multitapped second delay line to delay the rectangular wave train by selectable predetermined period. A control signal is formed which when fed into the generator produces a second rectangular wave train with a clock cycle period equal to the rectangular wave train clock cycle period plus the period of the second selected predetermined delay. By serially connecting a multitapped third delay line in series with the second delay line and by providing a first switch to select one of the outputs from said third delay line, the clock cycle period of the clock system may be adjusted. Use of a multitapped delay line for the first delay line and the addition of a second switch for selection among the various delayed signals of the first delay line, enable selective adjustment of clock pulse width.

摘要翻译： 一种用于提供矩形波形或波列的时钟系统，每个波段具有可选择的预定时钟周期周期。 由发生器产生矩形波列，该发生器包括通过使用多重第二延迟线连接到逆变器的第一延迟线，以通过可选择的预定周期延迟矩形波列。 形成控制信号，当馈送到发生器中时，产生具有等于矩形波列时钟周期周期的时钟周期周期加上第二选定预定延迟的周期的第二矩形波列。 通过串联连接与第二延迟线串联的多极化第三延迟线，并且通过提供第一开关来选择来自所述第三延迟线的输出之一，可以调整时钟系统的时钟周期周期。 对于第一延迟线使用多重延迟线和在第一延迟线的各种延迟信号之间添加用于选择的第二开关，使得能够选择性地调整时钟脉冲宽度。

公开(公告)号：US4348724A

公开(公告)日：1982-09-07

申请号：US140643

申请日：1980-04-15

申请人： David E. Cushing ,  Philip E. Stanley

发明人： David E. Cushing ,  Philip E. Stanley

IPC分类号： G06F9/28 ,  G06F9/22 ,  G06F9/26

CPC分类号： G06F9/265

摘要： A data processing system includes a first memory for storing microinstructions in a first plurality of storage locations and second memory for storing microinstructions in a second plurality of storage locations. A central processor executing a series of addressed microinstructions to control the functions performed by this system generates the address of the next microinstruction to be executed in series as well as a next address selection signal. Addressing circuitry concurrently applies the next address generated by the processor to address inputs of each of the first memory and the second memory. After a predetermined delay, either the first memory or the second memory is selected to output an address microinstruction responsive to the value of the next address selection signal.

摘要翻译： 数据处理系统包括用于存储第一多个存储位置中的微指令的第一存储器和用于在第二多个存储位置中存储微指令的第二存储器。 执行一系列寻址微指令以控制由该系统执行的功能的中央处理器产生要串行执行的下一个微指令的地址以及下一个地址选择信号。 寻址电路同时将由处理器产生的下一个地址应用于地址第一存储器和第二存储器中的每一个的输入。 在预定的延迟之后，选择第一存储器或第二存储器以响应于下一个地址选择信号的值来输出地址微指令。

公开(公告)号：US4099255A

公开(公告)日：1978-07-04

申请号：US749572

申请日：1976-12-10

申请人： Philip E. Stanley ,  William E. Woods

发明人： Philip E. Stanley ,  William E. Woods

IPC分类号： G06F9/48 ,  G06F1/04 ,  G06F11/00

CPC分类号： G06F9/4825

摘要： Interrupt service is enabled for either a real-time clock or watchdog timer time out condition. A mode register is provided to effectively enable or disable the interrupt apparatus and if enabled is coupled to enable a service register in response to repetitively occurring clock pulses. Each time the service register is enabled, a counter is changed in value until a predetermined value is indicated at which time interrupt service is enabled at an interrupt level specified by the operator. Further, facilities are provided for presetting the value of the counter in an expeditious manner.

摘要翻译： 中断服务启用了实时时钟或看门狗定时器超时条件。 提供模式寄存器以有效地启用或禁用中断装置，并且如果使能被耦合以使服务寄存器响应于重复出现的时钟脉冲。 每次服务寄存器被使能时，计数器的值被改变，直到指定了一个预定值，在该时间中断服务被允许在操作者指定的中断级别。 此外，还提供了一个快速预设柜台价值的设施。