Abstract:
A method (and system) for guaranteeing authenticity of an object, includes providing a sample of material obtainable only by at least one of chemical and physical processes such that the sample is random and not reproducible, associating a number reproducibly to the sample by using a specific reader, and forming at least one coded version of the number, the at least one coded version being obtained by a key signature, and the version being recorded into an area of the object.
Abstract:
The present invention provides a method and system for providing improved understandability of received speech characterized in that it includes input interface adapted to capture received speech signals connected to a speech recognition means for identifying the contents of the received speech connected to one input of a data processor adapted to perform improvement in understandability, a user profile storage connected to another input of said data processor for providing user specific improvement data, and an output generator connected to the output of said data processor to produce personalized output based on an individual's needs. The instant invention also provides a configured computer program product for carrying out the above method.
Abstract:
The present invention involves a method for generating a partial Cyclic Redundancy Checking (CRC) value of a first interval of data in a digital data stream. The method includes the step of loading a precomputed CRC value corresponding to a one bit followed by a predetermined number of zeros. The predetermined number of zeros correspond to the number of digits of a polynomial minus one. The first interval of data is partitioned into a plurality of bits. The precomputed CRC value corresponding to the one bit followed by the predetermined number of zeros is enabled, for each of the plurality of bits having a value of one. The enabled, precomputed CRC values are combined to generate the partial CRC value of the first interval of data. Advantageously, multiple copies of the process may be executed in parallel to achieve a large speed-up.
Abstract:
A crossbar is implemented within multimedia facilities of a processor to perform vector permute operations, in which the bytes of a source operand are reordered in the target output. The crossbar is then reused for other instructions requiring multiplexing or shifting operations, particularly those in which the size of additional multiplexers or the size and delay of a barrel shifter is significant. A wide shift operation, for example, may be performed with one cycle latency by the crossbar and one additional layer of multiplexers or a small barrel shifter. The crossbar facility thus gets reused with improved performance of the instructions now sharing the crossbar and a reduction in the total area required by a multimedia facility within a processor.
Abstract:
A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (10) prefetches data elements of a vector into the first memory prior to processing such data elements. If a requested data element is not present in the first memory, a load request is issued to the second memory and to lower levels of the memory hierarchy until the requested data element is finally retrieved and stored in the first memory. The data processor (10) continues to prefetch subsequent data elements of the vector by considering the length of the data element and the stride of the vector. In one embodiment, the data processor (10) prefetches the vector into the first memory in response to a single data stream touch load (DST) instruction (100).
Abstract:
A central processing unit (CPU) in a computer that permits speculative parallel execution of more than one instruction thread. The CPU uses Fork-Suspend instructions that are added to the instruction set of the CPU, and are inserted in a program prior to run-time to delineate potential future threads for parallel execution. The CPU has an instruction cache with one or more instruction cache ports, a bank of one or more program counters, a bank of one or more dispatchers, a thread management unit that handles inter-thread communications and discards future threads that violate dependencies, a set of architectural registers common to all threads, and a scheduler that schedules parallel execution of the instructions on one or more functional units in the CPU.
Abstract:
The computer processing unit of the present invention includes a new prefetch instruction, referred to as an STOUCH instruction, which provides the capability to encode compile-time speculations associated with the conditional branches between the time the prefetch request is initiated and the time the prefetched data is actually needed. As a result of this explicit communication of compile-time speculations to the run-time hardware, prefetched lines based on invalid speculations can be discarded earlier, whereas, prefetched lines based on valid speculations can be retained longer in the cache, leading to better cache performance.
Abstract:
The present invention relates to a method, system and computer program product for enabling the remote authentication of fingerprints over an insecure network using a client-server architecture by generation of a set of random queries relating to fingerprint patterns based on stored fingerprint data at the server, to which the client responds based on the observed fingerprint patterns, followed by the issuing of a randomly generates set of challenges pertaining to geometrical relationships between the fingerprint patterns for which confirm responses are received by their server, the final authentication being determined by the proportion of correct responses by the client to said challenges.
Abstract:
A method for data embedding in a digital image under the constraint of a pre-specified upper bound value on the amount of change in the value of a property associated with the image. For compression tolerant data hiding in digital images, a property is selected in which the required information can be embedded. The property should be such that the value obtained from the property before and after a lossy compression does not change by a significant amount, and the change should be bounded. The property should be such that a property value as obtained from the image will not vary due to compression, but only due to malicious tampering. The value obtained from the property is stored so that the image can be verified. The complete image is considered in deciding whether to increase or decrease the property value in a particular region. The method also takes into account the fact that blocks having values of 0 or L, corresponding to the minimum and maximum property values, respectively, are incapable of change in a particular region. The method also attempts to vary even the checksum (stored information), in addition to modifying the image so that the net resultant checksum and the modified image coincide with each other.
Abstract:
A crossbar is implemented within multimedia facilities of a processor to perform vector permute operations, in which the bytes of a source operand are reordered in the target output. The crossbar is then reused for other instructions requiring multiplexing or shifting operations, particularly those in which the size of additional multiplexers or the size and delay of a barrel shifter is significant. A wide shift operation, for example, may be performed with one cycle latency by the crossbar and one additional layer of multiplexers or a small barrel shifter. The crossbar facility thus gets reused with improved performance of the instructions now sharing the crossbar and a reduction in the total area required by a multimedia facility within a processor.