中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

19 records (took 0.016 seconds)

    Combinatorial process optimization methodology and system
    12.
    发明授权
    Combinatorial process optimization methodology and system 有权
    组合过程优化方法和系统

    公开(公告)号：US08065107B1

    公开(公告)日：2011-11-22

    申请号：US12248850

    申请日：2008-10-09

    Applicant: Prashant B. Phatak

    Inventor： Prashant B. Phatak

    IPC: G01L15/00

    CPC classification number: G05B19/41865 ,  G05B2219/32015 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/26

    Abstract: A method for obtaining an optimized process solution from a set of design of experiments in a cost effective manner is provided. An actual experiment is performed and data from the experiments is obtained. Through statistical analysis of the data, coefficients are obtained. These coefficients are input into an experiment simulator where input parameters and conditions are combined with the coefficients to predict an output for the input parameters and conditions. From simulated results, conclusions can be drawn as to sets of input parameters and conditions providing desired results. Thereafter, physical experiments utilizing the input parameters and conditions may be performed to verify the simulated results.

    Abstract translation: 提供了一种以成本有效的方式从一组实验设计中获得优化的处理方案的方法。 执行实际实验并获得实验数据。 通过数据的统计分析，得到系数。 这些系数被输入到实验模拟器中，其中输入参数和条件与系数组合以预测输入参数和条件的输出。 从模拟结果可以得出结论，输入参数和条件的集合提供所需的结果。 此后，可以执行利用输入参数和条件的物理实验来验证模拟结果。

    Nonvolatile memory elements with metal-deficient resistive-switching metal oxides
    14.
    发明申请
    Nonvolatile memory elements with metal-deficient resistive-switching metal oxides 有权
    具有金属缺陷电阻开关金属氧化物的非易失性存储元件

    公开(公告)号：US20080219039A1

    公开(公告)日：2008-09-11

    申请号：US11714326

    申请日：2007-03-05

    Applicant: Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Prashant B. Phatak

    Inventor： Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Prashant B. Phatak

    IPC: G11C11/00

    CPC classification number: G11C13/0007 ,  G11C2213/32 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

    Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

    Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

    Closed loop sputtering controlled to enhance electrical characteristics in deposited layer
    15.
    发明授权
    Closed loop sputtering controlled to enhance electrical characteristics in deposited layer 有权
    控制闭环溅射以增强沉积层中的电特性

    公开(公告)号：US08895951B2

    公开(公告)日：2014-11-25

    申请号：US13249631

    申请日：2011-09-30

    Applicant: Wayne R French ,  Tony P. Chiang ,  Pragati Kumar ,  Prashant B Phatak

    Inventor： Wayne R French ,  Tony P. Chiang ,  Pragati Kumar ,  Prashant B Phatak

    IPC: H01L47/00 ,  C23C14/08 ,  C23C14/00 ,  C23C14/54 ,  H01L45/00 ,  H01L27/24

    CPC classification number: C23C14/083 ,  C23C14/0042 ,  C23C14/54 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

    Abstract: This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of an electrical property as a function of cathode voltage used during a sputtering process. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials, be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).

    Abstract translation: 本公开提供了制造半导体器件层和相关联的存储单元的方法。 经验数据可用于产生与金属 - 绝缘体 - 金属结构的沉积相关联的滞后曲线，其中曲线测量反映作为在溅射过程中使用的阴极电压的函数的电特性的变化。 通过在溅射过程中产生要使用的至少一个电压电平，其中电压从混合模式沉积中可获得的值中反映适合的电特性值，可以制造具有改进的特性和耐久性的半导体器件层。 根据该方法制造的这种电池的多电平存储器单元或阵列可以针对一组给定材料制造为具有最小的泄漏或“截止”电流特性（分别为Ileak或Ioff）或最大“on” 电流“off”电流（Ion / Ioff）。

    High Productivity Combinatorial Dual Shadow Mask Design
    16.
    发明申请
    High Productivity Combinatorial Dual Shadow Mask Design 有权
    高效率组合双阴影面具设计

    公开(公告)号：US20130093049A1

    公开(公告)日：2013-04-18

    申请号：US13275822

    申请日：2011-10-18

    Applicant: Venkat Ananthan ,  Prashant B. Phatak

    Inventor： Venkat Ananthan ,  Prashant B. Phatak

    IPC: H01L29/92 ,  H01L21/02

    CPC classification number: H01L27/3295 ,  C23C14/042 ,  H01L22/34 ,  H01L28/60 ,  H01L29/94

    Abstract: Dual shadow mask design can overcome the size and resolution limitations of shadow masks to provide capacitor structures with small effective areas. The capacitor structures have bottom and top electrode layers patterned using shadow masks, sandwiching a dielectric layer. The effective areas of the capacitors are the overlapping areas of the top and bottom electrodes, thus allowing small area sizes without subjected to the size limitation of the electrodes. The dual shadow mask design can be used in conjunction with high productivity combinatorial processes for screening and optimizing dielectric materials and fabrication processes.

    Abstract translation: 双荫罩设计可以克服荫罩的尺寸和分辨率限制，为电容器结构提供小的有效面积。 电容器结构具有使用荫罩图案化的底部和顶部电极层，夹持电介质层。 电容器的有效面积是顶部和底部电极的重叠区域，从而允许小面积尺寸而不受电极的尺寸限制。 双荫罩设计可以与高生产率组合工艺结合使用，用于筛选和优化电介质材料和制造工艺。

    Combinatorial Process Optimization Methodology and System
    18.
    发明申请
    Combinatorial Process Optimization Methodology and System 失效
    组合过程优化方法与系统

    公开(公告)号：US20120035878A1

    公开(公告)日：2012-02-09

    申请号：US13274621

    申请日：2011-10-17

    Applicant: Prashant B. Phatak

    Inventor： Prashant B. Phatak

    IPC: G06F19/00

    CPC classification number: G05B19/41865 ,  G05B2219/32015 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/26

    Abstract: A method for obtaining an optimized process solution from a set of design of experiments in a cost effective manner is provided. An actual experiment is performed and data from the experiments is obtained. Through statistical analysis of the data, coefficients are obtained. These coefficients are input into an experiment simulator where input parameters and conditions are combined with the coefficients to predict an output for the input parameters and conditions. From simulated results, conclusions can be drawn as to sets of input parameters and conditions providing desired results. Thereafter, physical experiments utilizing the input parameters and conditions may be performed to verify the simulated results.

    Abstract translation: 提供了一种以成本有效的方式从一组实验设计中获得优化的处理方案的方法。 执行实际实验并获得实验数据。 通过数据的统计分析，得到系数。 这些系数被输入到实验模拟器中，其中输入参数和条件与系数组合以预测输入参数和条件的输出。 从模拟结果可以得出结论，输入参数和条件的集合提供所需的结果。 此后，可以执行利用输入参数和条件的物理实验来验证模拟结果。

    Methods for forming nonvolatile memory elements with resistive-switching metal oxides
    19.
    发明申请
    Methods for forming nonvolatile memory elements with resistive-switching metal oxides 有权
    用电阻式开关金属氧化物形成非易失性存储元件的方法

    公开(公告)号：US20080220601A1

    公开(公告)日：2008-09-11

    申请号：US11714334

    申请日：2007-03-05

    Applicant: Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

    Inventor： Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

    IPC: H01L21/20 ,  H01L21/4763

    CPC classification number: H01L45/04 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

    Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

    Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

Patent Agency Ranking