公开(公告)号：US08895951B2

公开(公告)日：2014-11-25

申请号：US13249631

申请日：2011-09-30

申请人： Wayne R French ,  Tony P. Chiang ,  Pragati Kumar ,  Prashant B Phatak

发明人： Wayne R French ,  Tony P. Chiang ,  Pragati Kumar ,  Prashant B Phatak

IPC分类号： H01L47/00 ,  C23C14/08 ,  C23C14/00 ,  C23C14/54 ,  H01L45/00 ,  H01L27/24

CPC分类号： C23C14/083 ,  C23C14/0042 ,  C23C14/54 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

摘要： This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of an electrical property as a function of cathode voltage used during a sputtering process. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials, be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).

摘要翻译： 本公开提供了制造半导体器件层和相关联的存储单元的方法。 经验数据可用于产生与金属 - 绝缘体 - 金属结构的沉积相关联的滞后曲线，其中曲线测量反映作为在溅射过程中使用的阴极电压的函数的电特性的变化。 通过在溅射过程中产生要使用的至少一个电压电平，其中电压从混合模式沉积中可获得的值中反映适合的电特性值，可以制造具有改进的特性和耐久性的半导体器件层。 根据该方法制造的这种电池的多电平存储器单元或阵列可以针对一组给定材料制造为具有最小的泄漏或“截止”电流特性（分别为Ileak或Ioff）或最大“on” 电流“off”电流（Ion / Ioff）。

公开(公告)号：US08383430B2

公开(公告)日：2013-02-26

申请号：US13399719

申请日：2012-02-17

申请人： Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G Malhotra ,  Prashant B Phatak ,  Kurt H Weiner

发明人： Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G Malhotra ,  Prashant B Phatak ,  Kurt H Weiner

IPC分类号： H01L21/00

CPC分类号： G01R31/2831 ,  G01R31/2834 ,  H01L22/34

摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

摘要翻译： 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

公开(公告)号：US08344375B2

公开(公告)日：2013-01-01

申请号：US13312061

申请日：2011-12-06

申请人： Nitin Kumar ,  Tony Chiang ,  Chi-I Lang ,  Prashant B Phatak ,  Jinhong Tong

发明人： Nitin Kumar ,  Tony Chiang ,  Chi-I Lang ,  Prashant B Phatak ,  Jinhong Tong

IPC分类号： H01L29/12 ,  H01L29/02

CPC分类号： G11C13/0007 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

摘要： Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

摘要翻译： 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

公开(公告)号：US08369131B2

公开(公告)日：2013-02-05

申请号：US13286472

申请日：2011-11-01

申请人： Yun Wang ,  Prashant B Phatak ,  Tony Chiang

发明人： Yun Wang ,  Prashant B Phatak ,  Tony Chiang

IPC分类号： G11C11/00 ,  G11C11/36

CPC分类号： G11C13/02 ,  G11C7/00 ,  G11C11/36 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0069 ,  G11C13/04 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72

摘要： According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.