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11.发明授权Method and apparatus for configuring a memory device and a memory channel using configuration space registers 失效使用配置空间寄存器配置存储器件和存储器通道的方法和装置公开(公告)号：US06378056B2
公开(公告)日：2002-04-23
申请号：US09186050
申请日：1998-11-03
IPC分类号： G06F1200
CPC分类号： G11C7/20
摘要： A method and apparatus for configuring memory devices. A disclosed bus controller includes a storage location and a control circuit. The control circuit is coupled to perform an initialization operation when a value indicating that initialization operation is stored in the storage location. The initialization operation is selected from one of a set of initialization operations that the control circuit is capable of performing.
摘要翻译： 一种用于配置存储器件的方法和装置。 所公开的总线控制器包括存储位置和控制电路。 当指示初始化操作存储在存储位置中的值时，控制电路被耦合以执行初始化操作。 从控制电路能够执行的一组初始化操作中选择初始化操作。
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12.发明授权Method and apparatus for configuring and initializing a memory device and a memory channel 有权用于配置和初始化存储器件和存储器通道的方法和装置公开(公告)号：US06226729B1
公开(公告)日：2001-05-01
申请号：US09186051
申请日：1998-11-03
IPC分类号： G06F1200
CPC分类号： G06F13/4243
摘要： A method and apparatus for configuring and/or initializing memory devices. A disclosed method initializes a memory controller and a plurality of memory controller configuration registers. Serial identification numbers are assigned to memory devices coupled to the memory controller. Additionally, groups of device identification numbers, which are based at least in part on the memory device sizes, are assigned to the memory devices, and the memory devices are enabled.
摘要翻译： 一种用于配置和/或初始化存储器件的方法和装置。 所公开的方法初始化存储器控制器和多个存储器控制器配置寄存器。 串行识别号被分配给耦合到存储器控制器的存储器件。 此外，至少部分地基于存储器设备大小的设备标识号码组被分配给存储器设备，并且存储器设备被使能。
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13.发明授权Method and apparatus for restoring a memory device channel when exiting a low power state 有权当退出低功率状态时恢复存储器件通道的方法和装置公开(公告)号：US06230274B1
公开(公告)日：2001-05-08
申请号：US09186049
申请日：1998-11-03
IPC分类号： G06F126
CPC分类号： G06F11/1441
摘要： A method and apparatus for restoring a memory device channel when exiting a low power state. One method involves storing a set of memory initialization values from storage locations in a memory controller into a memory that maintains values during a power down state. The values may be necessary to access a system memory. When the power down state is exited, the values are restored to the storage locations in the memory controller.
摘要翻译： 一种当退出低功率状态时恢复存储器件通道的方法和装置。 一种方法涉及将存储器初始化值的集合存储在存储器控制器中的存储位置到在断电状态期间维持值的存储器中。 这些值可能需要访问系统内存。 当退出掉电状态时，这些值将恢复到存储器控制器中的存储位置。
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公开(公告)号：US06212611B1
公开(公告)日：2001-04-03
申请号：US09186045
申请日：1998-11-03
IPC分类号： G06F1300
CPC分类号： G06F13/1626
摘要： A pipelined memory controller that includes a decode stage, and a schedule stage, wherein the schedule stage includes a command queue to store multiple commands. In one embodiment, the schedule stage further includes look ahead logic which can modify an order memory commands are stored in the command queue.
摘要翻译： 包括解码级和调度级的流水线存储器控制器，其中调度级包括用于存储多个命令的命令队列。 在一个实施例中，调度阶段还包括可以修改订单存储器命令存储在命令队列中的前瞻逻辑。
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15.发明授权Symmetric multiprocessing system with unified environment and distributed system functions 失效具有统一环境和分布式系统功能的对称多处理系统
公开(公告)号：US06047355A
公开(公告)日：2000-04-04
申请号：US814606
申请日：1997-03-10
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368 , G06F13/00
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.
摘要翻译： 具有统一环境和分布式系统功能的对称多处理系统为系统中的所有功能单元提供统一的地址空间，同时在系统的功能单元上分配各种系统功能的执行，每个功能单元承担其自身方面的责任 操作。 此外，该系统提供改进的系统总线操作，用于从存储器传输数据。
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16.发明授权System having independently addressable bus interfaces coupled to serially connected multi-ported signal distributors generating and maintaining frame based polling schedule favoring isochronous peripherals 失效具有耦合到串行连接的多端口信号分配器的独立可寻址总线接口的系统，其生成和维护基于帧的轮询时间表，有利于等时外设
公开(公告)号：US5615404A
公开(公告)日：1997-03-25
申请号：US332255
申请日：1994-10-31
申请人： Shaun Knoll , Jeff C. Morriss , Shelagh Callahan , Ajay V. Bhatt , Puthiya K. Nizar , Richard M. Haslam , Andrew M. Volk , Sudarshan B. Cadambi
发明人： Shaun Knoll , Jeff C. Morriss , Shelagh Callahan , Ajay V. Bhatt , Puthiya K. Nizar , Richard M. Haslam , Andrew M. Volk , Sudarshan B. Cadambi
CPC分类号： H04L12/40058 , G06F13/423 , H04L12/40078
摘要： A bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces are provided for form an hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system. The bus controller, bus signal distributors, and bus interfaces are provided with circuitry and complementary logic for implementing a master/slave model of flow control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave "devices", employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.
摘要翻译： 总线控制器，多个1：n总线信号分配器和多个总线接口被提供用于形成用于将多个等时和异步外设串行连接到计算机系统的系统单元的分层串行总线组件。 总线控制器，总线信号分配器和总线接口具有用于实现流量控制的主/从模型的电路和互补逻辑，用于将总线代理相互连接以进行数据通信事务。 在某些实施例中，这些电路和互补逻辑还进行采用流量控制的主/从模型的连接管理事务，实现用于轮询从设备的基于帧的轮询调度，使用至少两个地址空间来进行各种交易 支持基于通信分组的事务，和/或电表示数据和/或控制状态。
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