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公开(公告)号：US20240171074A1
公开(公告)日：2024-05-23
申请号：US18493826
申请日：2023-10-25
Applicant: Richtek Technology Corporation
Inventor： Jiing-Horng Wang , Yu-Pin Tseng , Chia-Jung Chang , Tsan-He Wang , Shao-Ming Chang
IPC: H02M3/158
CPC classification number: H02M3/158 , H02M3/33507
Abstract: A switching regulator includes: a power stage circuit, a control circuit and an operation clock signal generator circuit. The operation clock signal generator circuit includes: a time point option unit generating a time point option signal according to a phase node voltage during a ringing period subsequent to a blanking period, to indicate at least one available turn-on time point, or generating a lowest voltage time point signal according to the phase node voltage during a tolerance period, to indicate a lowest voltage time point; and a time point deciding unit deciding the tolerance period according to a base clock signal and a tolerable frequency range and select the available turn-on time point or the lowest voltage time point within the tolerance period as a decided time point, to generate the operation clock signal.
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12.发明公开公开(公告)号：US20240128868A1
公开(公告)日：2024-04-18
申请号：US18471331
申请日：2023-09-21
Applicant: Richtek Technology Corporation
Inventor： Chia-Jung Chang , Shao-Ming Chang , Tsan-He Wang , Jiing-Horng Wang , Yu-Pin Tseng
Abstract: A switching regulator includes: a power stage circuit; a control circuit; and an operation clock signal generator circuit configured to generate plural test clock signals during a clock determination period and generate an operation clock signal during a normal operation period. When the switching regulator operates during the clock determination period in a discontinuous conduction mode, the control circuit alternatingly generates plural PWM signals corresponding to the test clock signals generated by the operation clock signal generator circuit and an output voltage, wherein each PWM signal corresponds to one test clock signal, so that the power stage circuit generates corresponding phase node voltages at a phase node, wherein among the plural test clock signals, the operation clock signal generator circuit selects one test clock signal corresponding to a minimum phase node voltage as the operation clock signal during the normal operation period.
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公开(公告)号：US20240128853A1
公开(公告)日：2024-04-18
申请号：US18145267
申请日：2022-12-22
Applicant: Richtek Technology Corporation
Inventor： Jung-Sheng CHEN , Chih-Chun CHUANG , Yong-Chin LEE
Abstract: A power converter that properly copes with the wiring defects on a feedback path is shown. According to a control signal, a power driver couples an input voltage to an energy storage element to provide an output voltage that is down-converted from the input voltage. The output voltage is further converted into a feedback voltage by a feedback circuit, and is entered to an error amplifier with a reference voltage for generation of an amplified error. A control signal generator generates the control signal of the power driver according to the amplified error. The power converter specifically has a comparator, which is enabled in a soft-start stage till the output voltage reaches a stable status. The comparator compares the amplified error with a critical value. When the amplified error exceeds the critical value, the input voltage is disconnected from the energy storage element.
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公开(公告)号：US20240120846A1
公开(公告)日：2024-04-11
申请号：US18300530
申请日：2023-04-14
Applicant: Richtek Technology Corporation
Inventor： Yu-Chang Chen , Ta-Yung Yang , Kun-Yu Lin , Hsin-Yi Wu
CPC classification number: H02M3/33571 , H02M1/083 , H02M3/01
Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. During a DCM (discontinuous conduction mode) operation, the second driving signal includes a resonant pulse for demagnetizing the transformer and a ZVS (zero voltage switching) pulse for achieving ZVS of the first transistor. The resonant pulse is skipped when the output voltage is lower than a low-voltage threshold.
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15.发明公开公开(公告)号：US20240030297A1
公开(公告)日：2024-01-25
申请号：US18314684
申请日：2023-05-09
Applicant: Richtek Technology Corporation
Inventor： Chin-Chin Tsai , Han-Chung Tai , Yong-Zhong Hu
IPC: H01L29/417 , H01L29/423 , H01L29/40
CPC classification number: H01L29/41725 , H01L29/42376 , H01L29/401
Abstract: An integrated structure of semiconductor devices having a shared contact plug includes: a first device, a second device and a shared contact plug. The first device includes a first gate having a conduction region, two spacer regions and a protection region. The two spacer regions overlay and are connected with two ends of the conductive region, respectively. The protection region overlays and is connected with the spacer region located outside a shared side of the conductive region. The second device includes a shared region, wherein the shared region is located in a semiconductor layer which is located below and outside the protection region. The shared contact plug is formed on and in contact with the conductive region and the shared region. The first gate is electrically connected with the shared region through the shared contact plug, wherein the shared contact plug overlays and is connected with the protection region.
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Patent Agency Ranking
16.发明公开公开(公告)号：US20240014154A1
公开(公告)日：2024-01-11
申请号：US18186974
申请日：2023-03-21
Applicant: Richtek Technology Corporation
Inventor： Wu-Te WENG , Yong-Zhong HU
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/02 , H01L24/03 , H01L2224/02381 , H01L2224/05548 , H01L2224/05567 , H01L2224/05124 , H01L2224/05147 , H01L2224/05624 , H01L2224/0239 , H01L2924/01013 , H01L2224/05085 , H01L2224/03462 , H01L2224/0391
Abstract: A semiconductor device with a pad structure resistant to plasma damage includes: a main pad portion including main conductor units and main via units; a sub-pad portion including sub-conductor units and sub-via units; a pad bonding unit in direct contact with and in connection with a top main conductor unit, wherein the top main conductor unit is the main conductor unit formed in a top metal layer; and a bridge pad unit in direct contact with a top sub-conductor unit, wherein the top sub-conductor unit is the sub-conductor unit formed in the top metal layer. The bridge pad unit is in direct contact with the pad bonding unit. The main pad portion and sub-pad portion are located below the pad bonding unit and bridge pad unit respectively, and the main pad portion and the sub-pad portion are not in direct connection with each other.
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公开(公告)号：US11811319B2
公开(公告)日：2023-11-07
申请号：US17520637
申请日：2021-11-06
Applicant: Richtek Technology Corporation
Inventor： Tsung-Wei Huang , Shui-Mu Lin
CPC classification number: H02M3/158 , H02M1/0095 , H02M3/07
Abstract: A power conversion circuit includes an N-level PWM power converter and a switching capacitor power converter. The N-level PWM power converter includes shared switches shared with the switching capacitor power converter, and PWM switches. In an N-level PWM mode, the shared switches and the PWM switches periodically switch an inductor and a capacitor, to execute power conversion between a first power and a second power by N-level PWM switching operation. The switching capacitor power converter includes the shared switches and auxiliary switches. In a capacitive conversion mode, the shared switches and the auxiliary switches periodically switch the capacitor, to execute power conversion between the first power and the second power by capacitive power conversion operation. In the capacitive conversion mode, a portion of the plural PWM switches are always OFF such that one end of the inductor is floating.
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公开(公告)号：US11791722B2
公开(公告)日：2023-10-17
申请号：US17511645
申请日：2021-10-27
Applicant: Richtek Technology Corporation
Inventor： Tsung-Wei Huang , Ding-Yu Wei , Sheng-Kai Fan
Abstract: A switched capacitor converter circuit includes: plural capacitors and plural switches which switch the connections of the plural capacitors periodically. In a first period, the plural switches control a first capacitor to be electrically connected between a first power and a second power, and control a second capacitor and a third capacitor to be electrically connected in series between the second power and a ground level. In a second period, the plural switches control the first capacitor and the second capacitor to be electrically connected in series between the second power and the ground, and control the third capacitor and the second capacitor to be electrically connected in parallel with the second power, thereby a second current of the second power is 4 times of a first current of the first power.
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公开(公告)号：US11736013B2
公开(公告)日：2023-08-22
申请号：US17566678
申请日：2021-12-30
Applicant: Richtek Technology Corporation
Inventor： Shei-Chie Yang , Jian-Yu Tu , Yuan-Yen Mai , Pao-Hsun Yu
CPC classification number: H02M3/1582 , H02M1/009
Abstract: A buck-boost switching regulator includes: a power switch circuit including an input switch unit and an output switch unit which switch a first terminal and a second terminal of an inductor for buck-boost conversion; at least one low dropout regulator correspondingly coupled to at least one output high side switch in the output switch unit to correspondingly convert at least one low dropout voltage into at least one output voltage; and a bypass control circuit configured to operably generate a bypass control signal according to a conversion voltage difference between the input voltage and the corresponding low dropout voltage; wherein when the corresponding conversion voltage difference is lower than a reference voltage, the bypass control signal controls a corresponding bypass switch to electrically connect the input voltage with the corresponding low dropout node.
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20.发明公开公开(公告)号：US20230238242A1
公开(公告)日：2023-07-27
申请号：US17933126
申请日：2022-09-19
Applicant: Richtek Technology Corporation
Inventor： Chin-Chin Tsai , Yong-Zhong Hu
IPC: H01L21/28 , H01L29/49 , H01L21/768 , H01L49/02
CPC classification number: H01L21/28229 , H01L29/4916 , H01L21/76897 , H01L28/88
Abstract: A polysilicon-insulator-polysilicon (PIP) structure includes: a first polysilicon region formed on a substrate; a first insulation region formed outside one side of the first polysilicon region and adjoined to the first polysilicon region in a horizontal direction; and a second polysilicon region formed outside one side of the first insulation region. The first polysilicon region, the first insulation region and the second polysilicon region are adjoined in sequence in the horizontal direction. The second polysilicon region is formed outside the first insulation region by a first self-aligned process step, and the first insulation region is formed outside the first polysilicon region by a second self-aligned process step.
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