公开(公告)号：US5606347A

公开(公告)日：1997-02-25

申请号：US474640

申请日：1995-06-07

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: G06F12/02 ,  G09G5/02 ,  G09G5/39 ,  G09G5/04

CPC classification number: G09G5/39 ,  G06F12/0207 ,  G09G5/022 ,  G09G2352/00

Abstract: A memory device 72 is provided which includes a plurality of data storage locations each having an associated address and arranged as a plurality of planes 76. A data port 78, 86 is coupled to each of the planes 76. Control circuitry 78, 80, 82 is provided and includes inputs receiving an address and a mode control signal, the control circuitry operable in the first mode to provide access through data port 78, 86 to an addressed location in each of the plurality of planes 76 and in a second mode to provide access through the data port 78, 86 to a plurality of storage locations in a selected one of the planes 76.

Abstract translation: 提供存储器件72，其包括多个数据存储位置，每个存储位置具有相关联的地址并被布置为多个平面76.数据端口78,86耦合到每个平面76.控制电路78,80,82 并且包括接收地址和模式控制信号的输入，所述控制电路可在第一模式中操作以提供通过数据端口78,86到达多个平面76中的每一个中的寻址位置的访问，并且以第二模式提供 通过数据端口78,88访问所选择的一个平面76中的多个存储位置。

公开(公告)号：US5546553A

公开(公告)日：1996-08-13

申请号：US359324

申请日：1994-12-15

Applicant: Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

Inventor： Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

IPC: G06F3/14 ,  G09G1/16 ,  G09G5/00 ,  G09G5/06 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G06F12/00

CPC classification number: G06F3/1438 ,  G06F3/14 ,  G09G5/06 ,  G09G5/363 ,  G09G5/39 ,  G09G5/395 ,  G09G2360/126 ,  G09G5/001

Abstract: A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit. Other access circuits, devices, systems and methods are also described.

公开(公告)号：US4494187A

公开(公告)日：1985-01-15

申请号：US350960

申请日：1982-02-22

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: G06F9/32 ,  G06F12/06 ,  G11C17/12 ,  G06F13/00

CPC classification number: G06F12/0607 ,  G06F9/32 ,  G11C17/12

Abstract: A system for real-time digital processing employs a single-chip microcomputer device having a high-speed on-chip program ROM and a separate data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. The on-chip program ROM has a low-level precharge circuit with feedback to improve speed or access time.

Abstract translation: 一种用于实时数字处理的系统采用具有高速片上程序ROM和独立数据RAM的单片微机器件，具有用于程序和数据的单独的地址和数据路径。 外部程序地址总线允许在扩展模式下进行片外程序提取，外部数据总线返回操作码。 总线交换模块允许在特殊情况下在单独的内部程序和数据总线之间进行转移。 内部总线为16位，ALU和累加器为32位。 乘法器电路产生与ALU分离的单状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器。 片上程序ROM具有具有反馈的低电平预充电电路，以提高速度或访问时间。

公开(公告)号：US06839831B2

公开(公告)日：2005-01-04

申请号：US09733597

申请日：2000-12-08

Applicant: Keith Balmer ,  Richard D. Simpson ,  Iain Robertson ,  John Keay

Inventor： Keith Balmer ,  Richard D. Simpson ,  Iain Robertson ,  John Keay

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/355 ,  G06F9/38 ,  G06F9/28

CPC classification number: G06F9/3885 ,  G06F9/3001 ,  G06F9/3012 ,  G06F9/355 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3891

Abstract: A data processing apparatus includes first (78) and second (80) functional unit groups, each includes a plurality of functional units and a register file (76) comprising a plurality of registers. A comparator (181) receives the operand register number of a current instruction for a functional unit in the first functional unit group, and the destination register number of an immediately preceding instruction for the second functional unit group. A register file bypass multiplexer (174) selects the data from the register corresponding to the operand number of the current instruction on no match and selects the output of the second functional unit group (hotpath 172) if the comparator indicates a match. The first functional unit utilizes the output of the second functional unit group without waiting for the result to be stored in the register file.

Abstract translation: 数据处理装置包括第一（78）和第二（80）个功能单元组，每个功能单元组包括多个功能单元和包括多个寄存器的寄存器文件（76）。 比较器（181）接收第一功能单元组中的功能单元的当前指令的操作数寄存器号和第二功能单元组的紧接在前的指令的目的地寄存器号。 寄存器文件旁路多路复用器（174）在不匹配的情况下从当前指令的操作数编号对应的寄存器中选择数据，如果比较器指示匹配，则选择第二功能单元组（热路径172）的输出。 第一功能单元利用第二功能单元组的输出，而不等待结果存储在寄存器文件中。

公开(公告)号：US06189077B1

公开(公告)日：2001-02-13

申请号：US08476786

申请日：1995-06-07

Applicant: Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

Inventor： Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

IPC: G06F1200

CPC classification number: G06F9/30101 ,  G06F3/14 ,  G06F3/1438 ,  G06F9/3879 ,  G06F12/0284 ,  G09G5/001 ,  G09G5/06 ,  G09G5/14 ,  G09G5/363 ,  G09G5/39 ,  G09G5/395 ,  G09G2360/126

Abstract: An access circuit for data swapping between two computers and a computer system including the access circuit. Each computer including an address bus for supplying addresses and a data bus for transferring data. The access circuit includes a register file and two address decoder circuits. The register file has a plurality of storage locations for storing data. The register file has dual data ports capable of simultaneous data transfer via the first data port with a first data storage location and via the second data port with a second, different storage location. Each address decoder is connected to the address bus of a corresponding computer and the register file. The address decoders translate an address received on the address bus to a storage location of the register file. Two handshakes circuits are connected to respective address decoders and digital computers. The first and second address decoders are connected to each other. When the storage location of the first address decoder equals the storage location of the second address decoder, one of the handshake circuits signals the corresponding digital computer a memory waitstate or memory fault. At least one of the decoders is be programmable to position in the address space of the corresponding computer. At least one the address decoders includes an autoincrement circuit advances the accessed storage location within the register file to a next storage location upon each data transfer.

Abstract translation: 一种用于两个计算机之间的数据交换的访问电路和包括该访问电路的计算机系统。 每个计算机包括用于提供地址的地址总线和用于传送数据的数据总线。 访问电路包括寄存器文件和两个地址解码器电路。 寄存器文件具有用于存储数据的多个存储位置。 寄存器文件具有双数据端口，能够经由具有第一数据存储位置的第一数据端口并经由具有第二不同存储位置的第二数据端口同时进行数据传输。 每个地址解码器连接到相应计算机的地址总线和寄存器文件。 地址解码器将地址总线上接收的地址转换为寄存器文件的存储位置。 两个握手电路连接到相应的地址解码器和数字计算机。 第一和第二地址解码器彼此连接。 当第一地址解码器的存储位置等于第二地址解码器的存储位置时，其中一个握手电路向对应的数字计算机发送一个存储器状态或存储器故障信号。 至少一个解码器可编程为位于相应计算机的地址空间中。 至少一个地址解码器包括自动增量电路，在每次数据传送时，将所访问的寄存器文件中的存储位置提前到下一个存储位置。

公开(公告)号：US5696923A

公开(公告)日：1997-12-09

申请号：US474863

申请日：1995-06-07

Applicant: Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

Inventor： Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

IPC: G06F3/14 ,  G06F9/30 ,  G06F12/02 ,  G09G5/06 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G06F9/26 ,  G06F9/34 ,  G06F12/00

CPC classification number: G06F9/30101 ,  G06F12/0284 ,  G06F3/14 ,  G06F3/1438 ,  G06F9/3879 ,  G09G5/06 ,  G09G5/14 ,  G09G5/363 ,  G09G5/39 ,  G09G5/395 ,  G09G2360/126 ,  G09G5/001

Abstract: A computer graphics system includes a host computer and a graphics processor. The graphics processor includes a control register. When the graphics processor writes to the control register it simultaneously generates a predetermined address on a local address bus and supplies data on a local data bus identical to data to be written into the control register. A shadow register circuit connected to both the host computer and the graphics processor includes a shadow register and first and second address decoders. The first address decoder enables a write from a local data bus into the shadow register upon detection of the predetermined address. The second address decoder enables a read from the shadow register via a host data bus upon detection of the predetermined address on a host address bus. The shadow register optionally includes a message in plurality of bits and a message out plurality of bits, the first and second address decoders enabling message passing between the host computer and the graphics processor. The shadow register circuit optionally includes a host interrupt bit and a buffer circuit. The buffer circuit generates a host interrupt signal to the host computer if either the graphics processor generates a host interrupt signal or the host interrupt bit of the shadow register has a predetermined state.

Abstract translation: 计算机图形系统包括主计算机和图形处理器。 图形处理器包括一个控制寄存器。 当图形处理器向控制寄存器写入时，它同时在本地地址总线上产生一个预定的地址，并将数据提供给与写入控制寄存器的数据相同的本地数据总线上。 连接到主计算机和图形处理器的影子寄存器电路包括影子寄存器和第一和第二地址解码器。 第一地址解码器能够在检测到预定地址时从本地数据总线写入影子寄存器。 当检测到主机地址总线上的预定地址时，第二地址解码器能够经由主机数据总线从影子寄存器读取。 影子寄存器可选地包括多个比特的消息和多个比特的消息，第一和第二地址解码器使能主机计算机和图形处理器之间的消息传递。 影子寄存器电路可选地包括主机中断位和缓冲电路。 如果图形处理器产生主机中断信号或影子寄存器的主机中断位具有预定状态，则缓冲电路向主计算机产生主机中断信号。

公开(公告)号：US5517609A

公开(公告)日：1996-05-14

申请号：US563469

申请日：1990-08-06

Applicant: Andrew J. Guillemaud ,  Anthony M. Balistreri ,  Karl M. Guttag ,  Richard D. Simpson

Inventor： Andrew J. Guillemaud ,  Anthony M. Balistreri ,  Karl M. Guttag ,  Richard D. Simpson

IPC: G09G5/395 ,  G06F15/00

CPC classification number: G09G5/395

Abstract: A graphics display system includes a random access memory arranged with a split serial register and a multiplexer for coupling column of storage cells from the memory array to storage elements of the split serial register. Data stored in either a low half or a high half of the addresses of the memory array may be selectively coupled through the multiplexer to either a low half or a high half of the split serial register. For a tile oriented graphics display operation, this arrangement increases the number of choices of where within the random access memory array to store specific bits of the tile data to be displayed. Data representing a tile can be mapped into a single row of the random access memory array.

Abstract translation: 图形显示系统包括布置有分离串行寄存器的随机存取存储器和用于将来自存储器阵列的存储单元列耦合到分离串行寄存器的存储元件的多路复用器。 存储在存储器阵列的地址的低半或高半部的数据可以通过多路复用器选择性地耦合到分离串行寄存器的低半或高半。 对于面向瓦片的图形显示操作，这种布置增加了随机存取存储器阵列内的哪里的选择的数量，以存储待显示的瓦片数据的特定位。 表示瓦片的数据可以被映射到随机存取存储器阵列的单行中。

公开(公告)号：US5446651A

公开(公告)日：1995-08-29

申请号：US159349

申请日：1993-11-30

Applicant: Phillip Moyse ,  Derek Roskell ,  Richard D. Simpson

Inventor： Phillip Moyse ,  Derek Roskell ,  Richard D. Simpson

IPC: G06F7/52 ,  G06F9/302

CPC classification number: G06F7/5336 ,  G06F9/30014 ,  G06F9/30036 ,  G06F2207/382 ,  G06F2207/3828

Abstract: A multiplier (220) selectively multiplies either a pair of 2N bit digital numbers or two pair of N bit digital numbers. The multiplier (220) includes a first input encoding circuit (350), a second input encoding circuit (352), a number of partial product generators (353, 354, 356, 363, 364, 366) and a set of adders (355, 357, 365, 367, 368, 369). The first input encoder circuit (350) generates partial product control signals from a first data word holding either a first 2N bit number or a first pair of N bit numbers. The second input encoding circuit (352) generates partial product input signals to the partial product generators (353, 354, 356, 363, 364, 366) from a second data word holding either a second 2N bit number or a second pair of N bit numbers. A first set of adders (355, 357) forms a weighted first sum of the first set of partial products signals. A second set of adders (365, 367) forms a weighted second sum of said second set of partial product signals. A third adder ( 368) forms a weighted sum of the first and second sums. The multiplexer (369) forms an output from the third adder in the 2N by 2N multiplication mode and forms an output having least significant bits corresponding to the first sum and most significant bits corresponding to the second sum in the pair of N by N multiplications modes.

Abstract translation: 乘法器（220）选择性地将一对2N位数字数字或两对N位数字数字相乘。 乘法器（220）包括第一输入编码电路（350），第二输入编码电路（352），多个部分乘积产生器（353,354,356,363,364,366）和一组加法器（355） ，357,365,367,368,369）。 第一输入编码器电路（350）从保持第一2N位数或第一对N位数的第一数据字生成部分乘积控制信号。 第二输入编码电路（352）从保持第二2N位数或第二对N位的第二数据字产生部分乘积输入信号到部分积发生器（353,354,356,363,364,366） 数字。 第一组加法器（355,357）形成第一组部分乘积信号的加权第一和。 第二组加法器（365,367）形成所述第二组部分乘积信号的加权第二和。 第三加法器（368）形成第一和第二和的加权和。 多路复用器（369）以2N乘2N模式形成来自第三加法器的输出，并且形成具有对应于在N乘乘模式对中的第一和和对应于第二和的最低有效位的输出 。

公开(公告)号：US5311211A

公开(公告)日：1994-05-10

申请号：US765623

申请日：1991-09-25

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: G09G1/16 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39 ,  G09G1/02

CPC classification number: G09G5/39 ,  G09G2360/122

Abstract: Method and apparatus of providing a display on a raster-scanned screen (1) from data stored in a video random access memory (8) having row and column addresses (6,7) for the storage elements, wherein the display area of the screen (1) is divided into a plurality of identical rectangular areas or "tiles". Addressing of the video random access memory (8) is derived by converting the screen raster-scanning signals via conversion circuits (5) such that sequential addressing of entire rows of storage elements of the video random access memory (8) corresponds to a description of all of the rectangular areas in turn, wherein the number of rectangular areas across the screen width is not equal to an integral power of 2.

Abstract translation: 从存储在存储元件的行和列地址（6,7）的视频随机存取存储器（8）中的数据在光栅扫描屏幕（1）上提供显示的方法和装置，其中屏幕的显示区域 （1）被分成多个相同的矩形区域或“瓦片”。 通过经由转换电路（5）转换屏幕光栅扫描信号来导出视频随机存取存储器（8）的寻址，使得视频随机存取存储器（8）的存储元件的整行的顺序寻址对应于 所有的矩形区域依次，其中横跨屏幕宽度的矩形区域的数量不等于2的整数倍。

公开(公告)号：US5122738A

公开(公告)日：1992-06-16

申请号：US594517

申请日：1990-10-09

Applicant: Richard D. Simpson ,  Iain C. Robertson

Inventor： Richard D. Simpson ,  Iain C. Robertson

IPC: G01R31/3185

CPC classification number: G01R31/318541

Abstract: A digital data storage circuit for a digital signal processor which is capable of receiving asynchronous inputs and is such as to be testable by selectively configuring the storage circuits as a shift register enabling the entry and extraction of test data into the processor. The storage circuit includes two latch elements each formed by two complementary transistor inverter circuits connected in a positive feedback arrangement and in which the output current capability of the second inverter circuit is restricted to enable the latch element to change state in response to input signals applied to it. Asynchronous inputs are applied to a first latch element through switch means comprising a complementary transistor inverter responsive to a SET input in series with a transistor responsive to a CLEAR input. The complementary inverter is connected to the input of the first latch element through a series connected transistor. During testing the series connected transistor is blocked and the first latch element is connected in a two elements per bit shift register configuration with the second latch element by series connected transistors controlled by antiphase square waves.